Revert "[APInt] Fix a few places that use APInt::getRawData to operate within the normal API."
This reverts commit r301105, 4, 3 and 1, as a follow up of the previous revert, which broke even more bots. For reference: Revert "[APInt] Use operator<<= where possible. NFC" Revert "[APInt] Use operator<<= instead of shl where possible. NFC" Revert "[APInt] Use ashInPlace where possible." PR32754. llvm-svn: 301111
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@ -876,13 +876,6 @@ public:
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return *this;
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}
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/// \brief Left-shift assignment function.
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///
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/// Shifts *this left by shiftAmt and assigns the result to *this.
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///
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/// \returns *this after shifting left by ShiftAmt
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APInt &operator<<=(const APInt &ShiftAmt);
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/// @}
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/// \name Binary Operators
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/// @{
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@ -964,11 +957,7 @@ public:
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/// \brief Left-shift function.
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///
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/// Left-shift this APInt by shiftAmt.
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APInt shl(const APInt &ShiftAmt) const {
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APInt R(*this);
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R <<= ShiftAmt;
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return R;
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}
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APInt shl(const APInt &shiftAmt) const;
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/// \brief Rotate left by rotateAmt.
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APInt rotl(const APInt &rotateAmt) const;
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@ -1949,7 +1949,8 @@ bool MIParser::getHexUint(APInt &Result) {
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return true;
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StringRef V = S.substr(2);
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APInt A(V.size()*4, V, 16);
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Result = A.zextOrTrunc(A.getActiveBits());
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Result = APInt(A.getActiveBits(),
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ArrayRef<uint64_t>(A.getRawData(), A.getNumWords()));
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return false;
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}
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@ -5343,7 +5343,7 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
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APInt Mask = APInt::getHighBitsSet(OpSizeInBits, OpSizeInBits - c1);
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SDValue Shift;
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if (c2 > c1) {
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Mask <<= c2 - c1;
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Mask = Mask.shl(c2 - c1);
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SDLoc DL(N);
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Shift = DAG.getNode(ISD::SHL, DL, VT, N0.getOperand(0),
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DAG.getConstant(c2 - c1, DL, N1.getValueType()));
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@ -2589,7 +2589,7 @@ SDValue SelectionDAGLegalize::ExpandBITREVERSE(SDValue Op, const SDLoc &dl) {
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DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(I - J, dl, SHVT));
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APInt Shift(Sz, 1);
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Shift <<= J;
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Shift = Shift.shl(J);
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Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(Shift, dl, VT));
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Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp, Tmp2);
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}
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@ -158,7 +158,9 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_ConstantFP(SDNode *N, unsigned ResNo) {
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// and the low 64 bits here.
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if (DAG.getDataLayout().isBigEndian() &&
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CN->getValueType(0).getSimpleVT() == llvm::MVT::ppcf128) {
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APInt Val = CN->getValueAPF().bitcastToAPInt().rotl(64);
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uint64_t words[2] = { CN->getValueAPF().bitcastToAPInt().getRawData()[1],
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CN->getValueAPF().bitcastToAPInt().getRawData()[0] };
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APInt Val(128, words);
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return DAG.getConstant(Val, SDLoc(CN),
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TLI.getTypeToTransformTo(*DAG.getContext(),
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CN->getValueType(0)));
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@ -1058,10 +1060,10 @@ void DAGTypeLegalizer::ExpandFloatRes_ConstantFP(SDNode *N, SDValue &Lo,
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APInt C = cast<ConstantFPSDNode>(N)->getValueAPF().bitcastToAPInt();
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SDLoc dl(N);
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Lo = DAG.getConstantFP(APFloat(DAG.EVTToAPFloatSemantics(NVT),
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C.extractBits(64, 64)),
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APInt(64, C.getRawData()[1])),
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dl, NVT);
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Hi = DAG.getConstantFP(APFloat(DAG.EVTToAPFloatSemantics(NVT),
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C.extractBits(64, 0)),
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APInt(64, C.getRawData()[0])),
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dl, NVT);
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}
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@ -2323,8 +2323,8 @@ void SelectionDAG::computeKnownBits(SDValue Op, APInt &KnownZero,
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if (const APInt *ShAmt = getValidShiftAmountConstant(Op)) {
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computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, DemandedElts,
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Depth + 1);
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KnownZero <<= *ShAmt;
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KnownOne <<= *ShAmt;
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KnownZero = KnownZero << *ShAmt;
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KnownOne = KnownOne << *ShAmt;
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// Low bits are known zero.
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KnownZero.setLowBits(ShAmt->getZExtValue());
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}
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@ -4160,7 +4160,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
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auto SignExtendInReg = [&](APInt Val, llvm::EVT ConstantVT) {
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unsigned FromBits = EVT.getScalarSizeInBits();
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Val <<= Val.getBitWidth() - FromBits;
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Val.ashrInPlace(Val.getBitWidth() - FromBits);
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Val = Val.ashr(Val.getBitWidth() - FromBits);
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return getConstant(Val, DL, ConstantVT);
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};
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@ -1714,7 +1714,7 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
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bestWidth = width;
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break;
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}
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newMask <<= width;
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newMask = newMask << width;
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}
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}
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}
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@ -2981,7 +2981,7 @@ static SDValue BuildExactSDIV(const TargetLowering &TLI, SDValue Op1, APInt d,
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Flags.setExact(true);
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Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt, &Flags);
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Created.push_back(Op1.getNode());
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d.ashrInPlace(ShAmt);
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d = d.ashr(ShAmt);
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}
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// Calculate the multiplicative inverse, using Newton's method.
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@ -1565,7 +1565,7 @@ GenericValue Interpreter::executeBitCastInst(Value *SrcVal, Type *DstTy,
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Tmp = Tmp.zext(SrcBitSize);
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Tmp = TempSrc.AggregateVal[SrcElt++].IntVal;
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Tmp = Tmp.zext(DstBitSize);
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Tmp <<= ShiftAmt;
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Tmp = Tmp.shl(ShiftAmt);
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ShiftAmt += isLittleEndian ? SrcBitSize : -SrcBitSize;
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Elt.IntVal |= Tmp;
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}
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@ -844,7 +844,7 @@ APInt llvm::APIntOps::RoundDoubleToAPInt(double Double, unsigned width) {
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// Otherwise, we have to shift the mantissa bits up to the right location
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APInt Tmp(width, mantissa);
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Tmp <<= (unsigned)exp - 52;
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Tmp = Tmp.shl((unsigned)exp - 52);
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return isNeg ? -Tmp : Tmp;
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}
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@ -1128,10 +1128,9 @@ void APInt::lshrSlowCase(unsigned ShiftAmt) {
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/// Left-shift this APInt by shiftAmt.
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/// @brief Left-shift function.
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APInt &APInt::operator<<=(const APInt &shiftAmt) {
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APInt APInt::shl(const APInt &shiftAmt) const {
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// It's undefined behavior in C to shift by BitWidth or greater.
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*this <<= (unsigned)shiftAmt.getLimitedValue(BitWidth);
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return *this;
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return shl((unsigned)shiftAmt.getLimitedValue(BitWidth));
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}
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void APInt::shlSlowCase(unsigned ShiftAmt) {
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@ -1852,17 +1852,17 @@ static void getUsefulBitsFromBitfieldMoveOpd(SDValue Op, APInt &UsefulBits,
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OpUsefulBits = 1;
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if (MSB >= Imm) {
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OpUsefulBits <<= MSB - Imm + 1;
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OpUsefulBits = OpUsefulBits.shl(MSB - Imm + 1);
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--OpUsefulBits;
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// The interesting part will be in the lower part of the result
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getUsefulBits(Op, OpUsefulBits, Depth + 1);
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// The interesting part was starting at Imm in the argument
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OpUsefulBits <<= Imm;
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OpUsefulBits = OpUsefulBits.shl(Imm);
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} else {
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OpUsefulBits <<= MSB + 1;
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OpUsefulBits = OpUsefulBits.shl(MSB + 1);
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--OpUsefulBits;
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// The interesting part will be shifted in the result
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OpUsefulBits <<= OpUsefulBits.getBitWidth() - Imm;
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OpUsefulBits = OpUsefulBits.shl(OpUsefulBits.getBitWidth() - Imm);
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getUsefulBits(Op, OpUsefulBits, Depth + 1);
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// The interesting part was at zero in the argument
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OpUsefulBits.lshrInPlace(OpUsefulBits.getBitWidth() - Imm);
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@ -1892,7 +1892,7 @@ static void getUsefulBitsFromOrWithShiftedReg(SDValue Op, APInt &UsefulBits,
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if (AArch64_AM::getShiftType(ShiftTypeAndValue) == AArch64_AM::LSL) {
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// Shift Left
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uint64_t ShiftAmt = AArch64_AM::getShiftValue(ShiftTypeAndValue);
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Mask <<= ShiftAmt;
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Mask = Mask.shl(ShiftAmt);
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getUsefulBits(Op, Mask, Depth + 1);
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Mask.lshrInPlace(ShiftAmt);
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} else if (AArch64_AM::getShiftType(ShiftTypeAndValue) == AArch64_AM::LSR) {
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@ -1902,7 +1902,7 @@ static void getUsefulBitsFromOrWithShiftedReg(SDValue Op, APInt &UsefulBits,
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uint64_t ShiftAmt = AArch64_AM::getShiftValue(ShiftTypeAndValue);
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Mask.lshrInPlace(ShiftAmt);
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getUsefulBits(Op, Mask, Depth + 1);
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Mask <<= ShiftAmt;
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Mask = Mask.shl(ShiftAmt);
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} else
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return;
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@ -1930,13 +1930,13 @@ static void getUsefulBitsFromBFM(SDValue Op, SDValue Orig, APInt &UsefulBits,
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uint64_t Width = MSB - Imm + 1;
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uint64_t LSB = Imm;
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OpUsefulBits <<= Width;
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OpUsefulBits = OpUsefulBits.shl(Width);
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--OpUsefulBits;
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if (Op.getOperand(1) == Orig) {
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// Copy the low bits from the result to bits starting from LSB.
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Mask = ResultUsefulBits & OpUsefulBits;
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Mask <<= LSB;
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Mask = Mask.shl(LSB);
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}
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if (Op.getOperand(0) == Orig)
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@ -1947,9 +1947,9 @@ static void getUsefulBitsFromBFM(SDValue Op, SDValue Orig, APInt &UsefulBits,
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uint64_t Width = MSB + 1;
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uint64_t LSB = UsefulBits.getBitWidth() - Imm;
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OpUsefulBits <<= Width;
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OpUsefulBits = OpUsefulBits.shl(Width);
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--OpUsefulBits;
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OpUsefulBits <<= LSB;
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OpUsefulBits = OpUsefulBits.shl(LSB);
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if (Op.getOperand(1) == Orig) {
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// Copy the bits from the result to the zero bits.
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@ -124,7 +124,7 @@ void llvm::HexagonLowerToMC(const MCInstrInfo &MCII, const MachineInstr *MI,
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// FP immediates are used only when setting GPRs, so they may be dealt
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// with like regular immediates from this point on.
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auto Expr = HexagonMCExpr::create(
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MCConstantExpr::create(Val.bitcastToAPInt().getZExtValue(),
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MCConstantExpr::create(*Val.bitcastToAPInt().getRawData(),
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AP.OutContext),
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AP.OutContext);
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HexagonMCInstrInfo::setMustExtend(*Expr, MustExtend);
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@ -26717,8 +26717,8 @@ void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
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DAG.computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, Depth + 1);
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unsigned ShAmt = ShiftImm->getZExtValue();
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if (Opc == X86ISD::VSHLI) {
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KnownZero <<= ShAmt;
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KnownOne <<= ShAmt;
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KnownZero = KnownZero << ShAmt;
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KnownOne = KnownOne << ShAmt;
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// Low bits are known zero.
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KnownZero.setLowBits(ShAmt);
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} else {
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@ -31054,7 +31054,8 @@ static SDValue combineShiftLeft(SDNode *N, SelectionDAG &DAG) {
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N0.getOperand(1).getOpcode() == ISD::Constant) {
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SDValue N00 = N0.getOperand(0);
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APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
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Mask <<= N1C->getAPIntValue();
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const APInt &ShAmt = N1C->getAPIntValue();
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Mask = Mask.shl(ShAmt);
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bool MaskOK = false;
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// We can handle cases concerning bit-widening nodes containing setcc_c if
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// we carefully interrogate the mask to make sure we are semantics
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@ -31264,9 +31265,9 @@ static SDValue combineVectorShiftImm(SDNode *N, SelectionDAG &DAG,
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unsigned ShiftImm = ShiftVal.getZExtValue();
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for (APInt &Elt : EltBits) {
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if (X86ISD::VSHLI == Opcode)
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Elt <<= ShiftImm;
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Elt = Elt.shl(ShiftImm);
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else if (X86ISD::VSRAI == Opcode)
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Elt.ashrInPlace(ShiftImm);
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Elt = Elt.ashr(ShiftImm);
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else
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Elt.lshrInPlace(ShiftImm);
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}
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@ -378,7 +378,7 @@ static Value *simplifyX86immShift(const IntrinsicInst &II,
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for (unsigned i = 0; i != NumSubElts; ++i) {
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unsigned SubEltIdx = (NumSubElts - 1) - i;
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auto SubElt = cast<ConstantInt>(CDV->getElementAsConstant(SubEltIdx));
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Count <<= BitWidth;
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Count = Count.shl(BitWidth);
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Count |= SubElt->getValue().zextOrTrunc(64);
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}
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}
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@ -1562,7 +1562,7 @@ Value *InstCombiner::SimplifyDemandedVectorElts(Value *V, APInt DemandedElts,
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for (unsigned Lane = 0; Lane != NumLanes; ++Lane) {
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APInt LaneElts = OpUndefElts.lshr(InnerVWidthPerLane * Lane);
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LaneElts = LaneElts.getLoBits(InnerVWidthPerLane);
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LaneElts <<= InnerVWidthPerLane * (2 * Lane + OpNum);
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LaneElts = LaneElts.shl(InnerVWidthPerLane * (2 * Lane + OpNum));
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UndefElts |= LaneElts;
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}
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}
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