[MIPS GlobalISel] ClampScalar G_SHL, G_ASHR and G_LSHR
ClampScalar G_SHL, G_ASHR and G_LSHR to s32 for MIPS32. Differential Revision: https://reviews.llvm.org/D66533 llvm-svn: 370067
This commit is contained in:
Petar Avramovic
parent
1d93522056
commit
4a2a653288
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@ -89,7 +89,8 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
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getActionDefinitionsBuilder({G_SHL, G_ASHR, G_LSHR})
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.legalFor({{s32, s32}})
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.clampScalar(1, s32, s32);
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.clampScalar(1, s32, s32)
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.clampScalar(0, s32, s32);
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getActionDefinitionsBuilder(G_ICMP)
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.legalForCartesianProduct({s32}, {s32, p0})
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@ -24,6 +24,12 @@
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define void @shlv(i32, i32) {entry: ret void}
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define void @ashrv(i32, i32) {entry: ret void}
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define void @lshrv(i32, i32) {entry: ret void}
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define void @shl_i16() {entry: ret void}
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define void @ashr_i8() {entry: ret void}
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define void @lshr_i16() {entry: ret void}
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define void @shl_i64() {entry: ret void}
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define void @ashl_i64() {entry: ret void}
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define void @lshr_i64() {entry: ret void}
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...
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---
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@ -596,3 +602,252 @@ body: |
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RetRA implicit $v0
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...
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---
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name: shl_i16
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: shl_i16
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
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; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
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; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
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; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[AND]](s32)
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; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
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; MIPS32: $v0 = COPY [[COPY3]](s32)
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; MIPS32: RetRA implicit $v0
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%1:_(s32) = COPY $a0
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%0:_(s16) = G_TRUNC %1(s32)
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%2:_(s16) = G_CONSTANT i16 2
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%3:_(s16) = G_SHL %0, %2(s16)
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%4:_(s32) = G_ANYEXT %3(s16)
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$v0 = COPY %4(s32)
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RetRA implicit $v0
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...
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---
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name: ashr_i8
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: ashr_i8
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
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; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
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; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
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; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
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; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C2]](s32)
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; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C2]](s32)
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; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[AND]](s32)
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; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)
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; MIPS32: $v0 = COPY [[COPY3]](s32)
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; MIPS32: RetRA implicit $v0
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%1:_(s32) = COPY $a0
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%0:_(s8) = G_TRUNC %1(s32)
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%2:_(s8) = G_CONSTANT i8 2
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%3:_(s8) = G_ASHR %0, %2(s8)
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%4:_(s32) = G_ANYEXT %3(s8)
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$v0 = COPY %4(s32)
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RetRA implicit $v0
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...
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---
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name: lshr_i16
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: lshr_i16
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
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; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
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; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
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; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
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; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
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; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
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; MIPS32: $v0 = COPY [[COPY3]](s32)
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; MIPS32: RetRA implicit $v0
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%1:_(s32) = COPY $a0
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%0:_(s16) = G_TRUNC %1(s32)
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%2:_(s16) = G_CONSTANT i16 2
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%3:_(s16) = G_LSHR %0, %2(s16)
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%4:_(s32) = G_ANYEXT %3(s16)
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$v0 = COPY %4(s32)
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RetRA implicit $v0
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...
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---
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name: shl_i64
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1, $a2, $a3
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; MIPS32-LABEL: name: shl_i64
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; MIPS32: liveins: $a0, $a1, $a2, $a3
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
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; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
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; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
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; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
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; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
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; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY4]], [[C]]
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; MIPS32: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY4]]
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; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY4]](s32), [[C]]
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; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY4]](s32), [[C1]]
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; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY4]](s32)
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; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[SUB1]](s32)
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; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[COPY4]](s32)
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; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL1]]
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; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[SUB]](s32)
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; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
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; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C2]]
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; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[SHL]], [[C1]]
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; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
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; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C2]]
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; MIPS32: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s32), [[OR]], [[SHL2]]
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; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
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; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C2]]
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; MIPS32: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s32), [[COPY1]], [[SELECT1]]
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; MIPS32: $v0 = COPY [[SELECT]](s32)
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; MIPS32: $v1 = COPY [[SELECT2]](s32)
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; MIPS32: RetRA implicit $v0, implicit $v1
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%2:_(s32) = COPY $a0
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%3:_(s32) = COPY $a1
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%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
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%4:_(s32) = COPY $a2
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%5:_(s32) = COPY $a3
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%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
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%6:_(s64) = G_SHL %0, %1(s64)
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%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
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$v0 = COPY %7(s32)
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$v1 = COPY %8(s32)
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RetRA implicit $v0, implicit $v1
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...
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---
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name: ashl_i64
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1, $a2, $a3
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; MIPS32-LABEL: name: ashl_i64
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; MIPS32: liveins: $a0, $a1, $a2, $a3
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
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; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
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; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
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; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
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; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
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; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY4]], [[C]]
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; MIPS32: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY4]]
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; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY4]](s32), [[C]]
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; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY4]](s32), [[C1]]
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; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY1]], [[COPY4]](s32)
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; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[COPY4]](s32)
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; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[SUB1]](s32)
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; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
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; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
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; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[COPY1]], [[C2]](s32)
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; MIPS32: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[COPY1]], [[SUB]](s32)
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; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
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; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
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; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[OR]], [[ASHR2]]
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; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
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; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
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; MIPS32: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s32), [[COPY]], [[SELECT]]
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; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
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; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
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; MIPS32: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s32), [[ASHR]], [[ASHR1]]
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; MIPS32: $v0 = COPY [[SELECT1]](s32)
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; MIPS32: $v1 = COPY [[SELECT2]](s32)
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; MIPS32: RetRA implicit $v0, implicit $v1
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%2:_(s32) = COPY $a0
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%3:_(s32) = COPY $a1
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%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
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%4:_(s32) = COPY $a2
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%5:_(s32) = COPY $a3
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%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
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%6:_(s64) = G_ASHR %0, %1(s64)
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%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
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$v0 = COPY %7(s32)
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$v1 = COPY %8(s32)
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RetRA implicit $v0, implicit $v1
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...
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---
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name: lshr_i64
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1, $a2, $a3
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; MIPS32-LABEL: name: lshr_i64
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; MIPS32: liveins: $a0, $a1, $a2, $a3
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
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; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
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; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
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; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
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; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
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; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY4]], [[C]]
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; MIPS32: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY4]]
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; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY4]](s32), [[C]]
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; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY4]](s32), [[C1]]
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; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[COPY4]](s32)
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; MIPS32: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[COPY4]](s32)
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; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[SUB1]](s32)
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; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[SHL]]
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; MIPS32: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[SUB]](s32)
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; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
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; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C2]]
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; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[OR]], [[LSHR2]]
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; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
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; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C2]]
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; MIPS32: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s32), [[COPY]], [[SELECT]]
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; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
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; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C2]]
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; MIPS32: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s32), [[LSHR]], [[C1]]
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; MIPS32: $v0 = COPY [[SELECT1]](s32)
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; MIPS32: $v1 = COPY [[SELECT2]](s32)
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; MIPS32: RetRA implicit $v0, implicit $v1
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%2:_(s32) = COPY $a0
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%3:_(s32) = COPY $a1
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%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
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%4:_(s32) = COPY $a2
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%5:_(s32) = COPY $a3
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%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
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%6:_(s64) = G_LSHR %0, %1(s64)
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%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
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$v0 = COPY %7(s32)
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$v1 = COPY %8(s32)
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RetRA implicit $v0, implicit $v1
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...
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@ -235,3 +235,143 @@ entry:
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ret i32 %shr
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}
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define i16 @shl_i16(i16 %a) {
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; MIPS32-LABEL: shl_i16:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: ori $1, $zero, 2
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; MIPS32-NEXT: ori $2, $zero, 65535
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; MIPS32-NEXT: and $1, $1, $2
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; MIPS32-NEXT: sllv $2, $4, $1
|
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; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%shl = shl i16 %a, 2
|
||||
ret i16 %shl
|
||||
}
|
||||
|
||||
define i8 @ashr_i8(i8 %a) {
|
||||
; MIPS32-LABEL: ashr_i8:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: ori $1, $zero, 2
|
||||
; MIPS32-NEXT: ori $2, $zero, 255
|
||||
; MIPS32-NEXT: and $1, $1, $2
|
||||
; MIPS32-NEXT: sll $2, $4, 24
|
||||
; MIPS32-NEXT: sra $2, $2, 24
|
||||
; MIPS32-NEXT: srav $2, $2, $1
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%0 = ashr i8 %a, 2
|
||||
ret i8 %0
|
||||
}
|
||||
|
||||
define i16 @lshr_i16(i16 %a) {
|
||||
; MIPS32-LABEL: lshr_i16:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: ori $1, $zero, 2
|
||||
; MIPS32-NEXT: ori $2, $zero, 65535
|
||||
; MIPS32-NEXT: and $1, $1, $2
|
||||
; MIPS32-NEXT: and $2, $4, $2
|
||||
; MIPS32-NEXT: srlv $2, $2, $1
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%0 = lshr i16 %a, 2
|
||||
ret i16 %0
|
||||
}
|
||||
|
||||
define i64 @shl_i64(i64 %a, i64 %b) {
|
||||
; MIPS32-LABEL: shl_i64:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: addiu $sp, $sp, -8
|
||||
; MIPS32-NEXT: .cfi_def_cfa_offset 8
|
||||
; MIPS32-NEXT: ori $1, $zero, 32
|
||||
; MIPS32-NEXT: subu $2, $6, $1
|
||||
; MIPS32-NEXT: subu $3, $1, $6
|
||||
; MIPS32-NEXT: ori $8, $zero, 0
|
||||
; MIPS32-NEXT: sltu $1, $6, $1
|
||||
; MIPS32-NEXT: xor $9, $6, $8
|
||||
; MIPS32-NEXT: sltiu $9, $9, 1
|
||||
; MIPS32-NEXT: sllv $10, $4, $6
|
||||
; MIPS32-NEXT: srlv $3, $4, $3
|
||||
; MIPS32-NEXT: sllv $6, $5, $6
|
||||
; MIPS32-NEXT: or $3, $3, $6
|
||||
; MIPS32-NEXT: sllv $2, $4, $2
|
||||
; MIPS32-NEXT: ori $4, $zero, 1
|
||||
; MIPS32-NEXT: and $6, $1, $4
|
||||
; MIPS32-NEXT: movn $8, $10, $6
|
||||
; MIPS32-NEXT: and $1, $1, $4
|
||||
; MIPS32-NEXT: movn $2, $3, $1
|
||||
; MIPS32-NEXT: and $1, $9, $4
|
||||
; MIPS32-NEXT: movn $2, $5, $1
|
||||
; MIPS32-NEXT: sw $2, 4($sp) # 4-byte Folded Spill
|
||||
; MIPS32-NEXT: move $2, $8
|
||||
; MIPS32-NEXT: lw $3, 4($sp) # 4-byte Folded Reload
|
||||
; MIPS32-NEXT: addiu $sp, $sp, 8
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%shl = shl i64 %a, %b
|
||||
ret i64 %shl
|
||||
}
|
||||
|
||||
define i64 @ashl_i64(i64 %a, i64 %b) {
|
||||
; MIPS32-LABEL: ashl_i64:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: ori $1, $zero, 32
|
||||
; MIPS32-NEXT: subu $2, $6, $1
|
||||
; MIPS32-NEXT: subu $3, $1, $6
|
||||
; MIPS32-NEXT: ori $8, $zero, 0
|
||||
; MIPS32-NEXT: sltu $1, $6, $1
|
||||
; MIPS32-NEXT: xor $8, $6, $8
|
||||
; MIPS32-NEXT: sltiu $8, $8, 1
|
||||
; MIPS32-NEXT: srav $9, $5, $6
|
||||
; MIPS32-NEXT: srlv $6, $4, $6
|
||||
; MIPS32-NEXT: sllv $3, $5, $3
|
||||
; MIPS32-NEXT: or $3, $6, $3
|
||||
; MIPS32-NEXT: sra $6, $5, 31
|
||||
; MIPS32-NEXT: srav $2, $5, $2
|
||||
; MIPS32-NEXT: ori $5, $zero, 1
|
||||
; MIPS32-NEXT: and $10, $1, $5
|
||||
; MIPS32-NEXT: movn $2, $3, $10
|
||||
; MIPS32-NEXT: and $3, $8, $5
|
||||
; MIPS32-NEXT: movn $2, $4, $3
|
||||
; MIPS32-NEXT: and $1, $1, $5
|
||||
; MIPS32-NEXT: movn $6, $9, $1
|
||||
; MIPS32-NEXT: move $3, $6
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%shr = ashr i64 %a, %b
|
||||
ret i64 %shr
|
||||
}
|
||||
|
||||
define i64 @lshr_i64(i64 %a, i64 %b) {
|
||||
; MIPS32-LABEL: lshr_i64:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: ori $1, $zero, 32
|
||||
; MIPS32-NEXT: subu $2, $6, $1
|
||||
; MIPS32-NEXT: subu $3, $1, $6
|
||||
; MIPS32-NEXT: ori $8, $zero, 0
|
||||
; MIPS32-NEXT: sltu $1, $6, $1
|
||||
; MIPS32-NEXT: xor $9, $6, $8
|
||||
; MIPS32-NEXT: sltiu $9, $9, 1
|
||||
; MIPS32-NEXT: srlv $10, $5, $6
|
||||
; MIPS32-NEXT: srlv $6, $4, $6
|
||||
; MIPS32-NEXT: sllv $3, $5, $3
|
||||
; MIPS32-NEXT: or $3, $6, $3
|
||||
; MIPS32-NEXT: srlv $2, $5, $2
|
||||
; MIPS32-NEXT: ori $5, $zero, 1
|
||||
; MIPS32-NEXT: and $6, $1, $5
|
||||
; MIPS32-NEXT: movn $2, $3, $6
|
||||
; MIPS32-NEXT: and $3, $9, $5
|
||||
; MIPS32-NEXT: movn $2, $4, $3
|
||||
; MIPS32-NEXT: and $1, $1, $5
|
||||
; MIPS32-NEXT: movn $8, $10, $1
|
||||
; MIPS32-NEXT: move $3, $8
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%shr = lshr i64 %a, %b
|
||||
ret i64 %shr
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue