Add a special handling case for untyped CopyFromReg node in GetCostForDef() of ScheduleDAGRRList
llvm-svn: 173833
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@ -21,6 +21,7 @@
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
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#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/IR/DataLayout.h"
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@ -274,8 +275,17 @@ static void GetCostForDef(const ScheduleDAGSDNodes::RegDefIter &RegDefPos,
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// the expansion of custom DAG-to-DAG patterns.
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// the expansion of custom DAG-to-DAG patterns.
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if (VT == MVT::Untyped) {
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if (VT == MVT::Untyped) {
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const SDNode *Node = RegDefPos.GetNode();
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const SDNode *Node = RegDefPos.GetNode();
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unsigned Opcode = Node->getMachineOpcode();
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// Special handling for CopyFromReg of untyped values.
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if (!Node->isMachineOpcode() && Node->getOpcode() == ISD::CopyFromReg) {
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unsigned Reg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
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const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(Reg);
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RegClass = RC->getID();
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Cost = 1;
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return;
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}
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unsigned Opcode = Node->getMachineOpcode();
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if (Opcode == TargetOpcode::REG_SEQUENCE) {
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if (Opcode == TargetOpcode::REG_SEQUENCE) {
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unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
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unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
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const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
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const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
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