Add code to emulate LDRSB (literal) Arm instruction.
llvm-svn: 126789
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@ -6461,6 +6461,99 @@ EmulateInstructionARM::EmulateLDRSBImmediate (ARMEncoding encoding)
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return true;
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}
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// LDRSB (literal) calculates an address from the PC value and an immediate offset, loads a byte from memory,
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// sign-extends it to form a 32-bit word, and writes tit to a register.
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bool
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EmulateInstructionARM::EmulateLDRSBLiteral (ARMEncoding encoding)
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{
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#if 0
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if ConditionPassed() then
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EncodingSpecificOperations(); NullCheckIfThumbEE(15);
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base = Align(PC,4);
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address = if add then (base + imm32) else (base - imm32);
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R[t] = SignExtend(MemU[address,1], 32);
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#endif
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bool success = false;
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const uint32_t opcode = OpcodeAsUnsigned (&success);
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if (!success)
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return false;
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if (ConditionPassed ())
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{
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uint32_t t;
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uint32_t imm32;
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bool add;
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// EncodingSpecificOperations(); NullCheckIfThumbEE(15);
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switch (encoding)
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{
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case eEncodingT1:
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// if Rt == ’1111’ then SEE PLI;
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// t = UInt(Rt); imm32 = ZeroExtend(imm12, 32); add = (U == ’1’);
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t = Bits32 (opcode, 15, 12);
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imm32 = Bits32 (opcode, 11, 0);
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add = BitIsSet (opcode, 23);
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// if t == 13 then UNPREDICTABLE;
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if (t == 13)
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return false;
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break;
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case eEncodingA1:
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{
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// t == UInt(Rt); imm32 = ZeroExtend(imm4H:imm4L, 32); add = (U == ’1’);
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t = Bits32 (opcode, 15, 12);
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uint32_t imm4H = Bits32 (opcode, 11, 8);
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uint32_t imm4L = Bits32 (opcode, 3, 0);
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imm32 = (imm4H << 4) & imm4L;
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add = BitIsSet (opcode, 23);
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// if t == 15 then UNPREDICTABLE;
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if (t == 15)
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return false;
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break;
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}
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default:
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return false;
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}
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// base = Align(PC,4);
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uint64_t pc_value = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_ADDRESS,
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&success);
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if (!success)
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return false;
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uint64_t base = AlignPC (pc_value);
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// address = if add then (base + imm32) else (base - imm32);
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addr_t address;
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if (add)
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address = base + imm32;
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else
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address = base - imm32;
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// R[t] = SignExtend(MemU[address,1], 32);
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Register base_reg;
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base_reg.SetRegister (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC);
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EmulateInstruction::Context context;
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context.type = eContextRegisterLoad;
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context.SetRegisterPlusOffset (base_reg, address - base);
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uint64_t unsigned_data = MemURead (context, address, 1, 0, &success);
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if (!success)
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return false;
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int64_t signed_data = llvm::SignExtend64<8>(unsigned_data);
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if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, (uint64_t) signed_data))
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return false;
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}
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return true;
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}
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// Bitwise Exclusive OR (immediate) performs a bitwise exclusive OR of a register value and an immediate value,
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// and writes the result to the destination register. It can optionally update the condition flags based on
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// the result.
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@ -7836,6 +7929,7 @@ EmulateInstructionARM::GetARMOpcodeForInstruction (const uint32_t opcode)
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{ 0x0e5f00f0, 0x005f00b0, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDRHLiteral, "ldrh<c> <Rt>, <label>" },
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{ 0x0e5000f0, 0x001000b0, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDRHRegister, "ldrh<c> <Rt>,[<Rn>,+/-<Rm>]{!}" },
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{ 0x0e5000f0, 0x005000d0, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDRSBImmediate, "ldrsb<c> <Rt>, [<Rn>{,#+/-<imm8>}]" },
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{ 0x0e5f00f0, 0x005f00d0, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDRSBLiteral, "ldrsb<c> <Rt> <label>" },
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//----------------------------------------------------------------------
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// Store instructions
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@ -8082,6 +8176,7 @@ EmulateInstructionARM::GetThumbOpcodeForInstruction (const uint32_t opcode)
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{ 0xfff00fc0, 0xf8300000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateLDRHRegister, "ldrh<c>.w <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]" },
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{ 0xfff00000, 0xf9900000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateLDRSBImmediate, "ldrsb<c> <Rt>,[<Rn>,#<imm12>]" },
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{ 0xfff00800, 0xf9100800, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateLDRSBImmediate, "ldrsb<c> <Rt>,[<Rn>,#+/-<imm8>]" },
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{ 0xff7f0000, 0xf91f0000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateLDRSBLiteral, "ldrsb<c> <Rt>, <label>" },
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//----------------------------------------------------------------------
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// Store instructions
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