Fix DisassembleThumb2DPReg()'s handling of RegClass. Cannot hardcode GPRRegClassID.
Also add some test cases. rdar://problem/9189829 llvm-svn: 128304
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@ -1947,25 +1947,25 @@ static bool DisassembleThumb2DPReg(MCInst &MI, unsigned Opcode, uint32_t insn,
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OpIdx = 0;
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OpIdx = 0;
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assert(NumOps >= 2 &&
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assert(NumOps >= 2 &&
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OpInfo[0].RegClass == ARM::rGPRRegClassID &&
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OpInfo[0].RegClass > 0 &&
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OpInfo[1].RegClass == ARM::rGPRRegClassID &&
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OpInfo[1].RegClass > 0 &&
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"Expect >= 2 operands and first two as reg operands");
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"Expect >= 2 operands and first two as reg operands");
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// Build the register operands, followed by the optional rotation amount.
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// Build the register operands, followed by the optional rotation amount.
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bool ThreeReg = NumOps > 2 && OpInfo[2].RegClass == ARM::rGPRRegClassID;
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bool ThreeReg = NumOps > 2 && OpInfo[2].RegClass > 0;
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MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::rGPRRegClassID,
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MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
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decodeRs(insn))));
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decodeRs(insn))));
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++OpIdx;
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++OpIdx;
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if (ThreeReg) {
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if (ThreeReg) {
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MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::rGPRRegClassID,
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MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B,OpInfo[OpIdx].RegClass,
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decodeRn(insn))));
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decodeRn(insn))));
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++OpIdx;
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++OpIdx;
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}
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}
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MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::rGPRRegClassID,
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MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
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decodeRm(insn))));
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decodeRm(insn))));
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++OpIdx;
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++OpIdx;
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@ -172,3 +172,12 @@
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# CHECK: ldr.w r5, [r6, #30]
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# CHECK: ldr.w r5, [r6, #30]
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0x56 0xf8 0x1e 0x56
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0x56 0xf8 0x1e 0x56
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# CHECK: sel r7, r3, r5
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0xa3 0xfa 0x85 0xf7
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# CHECK: lsl.w r7, r3, r5
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0x03 0xfa 0x05 0xf7
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# CHECK: adds.w r7, r3, r5
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0x13 0xeb 0x05 0x07
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