Refactor the T1sIt encodings into a parent class to get rid of all of the "let"
statements. llvm-svn: 120512
This commit is contained in:
Bill Wendling
parent
97253e62e9
commit
4915f56669
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@ -708,18 +708,32 @@ def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
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// Arithmetic Instructions.
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//
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// Add with carry register
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let isCommutable = 1, Uses = [CPSR] in
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def tADC : T1sIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
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"adc", "\t$Rdn, $Rm",
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[(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>,
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T1DataProcessing<0b0101> {
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// A8.6.2
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// Helper classes to encode the various T1sIt patterns.
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class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: T1sIt<oops, iops, itin, opc, asm, pattern>,
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T1DataProcessing<opA> {
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bits<3> Rdn;
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bits<3> Rm;
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let Inst{5-3} = Rdn;
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let Inst{2-0} = Rm;
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let Inst{5-3} = Rm;
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let Inst{2-0} = Rdn;
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}
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class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: T1sIt<oops, iops, itin, opc, asm, pattern>,
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T1General<opA> {
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bits<3> Rdn;
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bits<8> imm8;
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let Inst{10-8} = Rdn;
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let Inst{7-0} = imm8;
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}
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// Add with carry register
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let isCommutable = 1, Uses = [CPSR] in
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def tADC : // A8.6.2
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T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
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"adc", "\t$Rdn, $Rm",
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[(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>;
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// Add immediate
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def tADDi3 : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, i32imm:$imm3), IIC_iALUi,
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@ -735,16 +749,11 @@ def tADDi3 : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, i32imm:$imm3), IIC_iALUi,
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let Inst{2-0} = Rd;
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}
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def tADDi8 : T1sIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8), IIC_iALUi,
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"add", "\t$Rdn, $imm8",
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[(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>,
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T1General<{1,1,0,?,?}> {
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// A8.6.4 T2
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bits<3> Rdn;
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bits<8> imm8;
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let Inst{10-8} = Rdn;
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let Inst{7-0} = imm8;
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}
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def tADDi8 : // A8.6.4 T2
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T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),
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IIC_iALUi,
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"add", "\t$Rdn, $imm8",
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[(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>;
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// Add register
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let isCommutable = 1 in
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@ -775,16 +784,11 @@ def tADDhirr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
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// AND register
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let isCommutable = 1 in
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def tAND : T1sIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iBITr,
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"and", "\t$Rdn, $Rm",
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[(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>,
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T1DataProcessing<0b0000> {
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// A8.6.12
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bits<3> Rdn;
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bits<3> Rm;
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let Inst{5-3} = Rm;
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let Inst{2-0} = Rdn;
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}
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def tAND : // A8.6.12
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T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
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IIC_iBITr,
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"and", "\t$Rdn, $Rm",
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[(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>;
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// ASR immediate
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def tASRri : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5), IIC_iMOVsi,
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@ -801,28 +805,18 @@ def tASRri : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5), IIC_iMOVsi,
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}
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// ASR register
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def tASRrr : T1sIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iMOVsr,
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"asr", "\t$Rdn, $Rm",
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[(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>,
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T1DataProcessing<0b0100> {
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// A8.6.15
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bits<3> Rdn;
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bits<3> Rm;
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let Inst{5-3} = Rm;
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let Inst{2-0} = Rdn;
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}
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def tASRrr : // A8.6.15
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T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
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IIC_iMOVsr,
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"asr", "\t$Rdn, $Rm",
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[(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>;
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// BIC register
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def tBIC : T1sIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iBITr,
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"bic", "\t$Rdn, $Rm",
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[(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>,
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T1DataProcessing<0b1110> {
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// A8.6.20
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bits<3> Rdn;
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bits<3> Rm;
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let Inst{5-3} = Rm;
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let Inst{2-0} = Rdn;
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}
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def tBIC : // A8.6.20
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T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
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IIC_iBITr,
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"bic", "\t$Rdn, $Rm",
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[(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>;
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// CMN register
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let isCompare = 1, Defs = [CPSR] in {
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@ -915,16 +909,11 @@ def tCMPzhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
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// XOR register
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let isCommutable = 1 in
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def tEOR : T1sIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iBITr,
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"eor", "\t$Rdn, $Rm",
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[(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>,
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T1DataProcessing<0b0001> {
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// A8.6.45
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bits<3> Rdn;
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bits<3> Rm;
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let Inst{5-3} = Rm;
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let Inst{2-0} = Rdn;
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}
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def tEOR : // A8.6.45
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T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
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IIC_iBITr,
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"eor", "\t$Rdn, $Rm",
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[(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>;
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// LSL immediate
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def tLSLri : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5), IIC_iMOVsi,
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@ -941,16 +930,11 @@ def tLSLri : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5), IIC_iMOVsi,
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}
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// LSL register
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def tLSLrr : T1sIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iMOVsr,
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"lsl", "\t$Rdn, $Rm",
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[(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>,
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T1DataProcessing<0b0010> {
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// A8.6.89
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bits<3> Rdn;
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bits<3> Rm;
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let Inst{5-3} = Rm;
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let Inst{2-0} = Rdn;
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}
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def tLSLrr : // A8.6.89
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T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
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IIC_iMOVsr,
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"lsl", "\t$Rdn, $Rm",
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[(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>;
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// LSR immediate
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def tLSRri : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5), IIC_iMOVsi,
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@ -967,16 +951,11 @@ def tLSRri : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5), IIC_iMOVsi,
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}
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// LSR register
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def tLSRrr : T1sIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iMOVsr,
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"lsr", "\t$Rdn, $Rm",
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[(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>,
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T1DataProcessing<0b0011> {
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// A8.6.91
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bits<3> Rdn;
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bits<3> Rm;
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let Inst{5-3} = Rm;
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let Inst{2-0} = Rdn;
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}
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def tLSRrr : // A8.6.91
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T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
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IIC_iMOVsr,
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"lsr", "\t$Rdn, $Rm",
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[(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>;
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// Move register
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let isMoveImm = 1 in
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@ -1018,16 +997,11 @@ def tMOVgpr2gpr : T1I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
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// multiply register
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let isCommutable = 1 in
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def tMUL : T1sIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iMUL32,
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"mul", "\t$Rdn, $Rm, $Rdn", /* A8.6.105 MUL Encoding T1 */
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[(set tGPR:$Rdn, (mul tGPR:$Rn, tGPR:$Rm))]>,
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T1DataProcessing<0b1101> {
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// A8.6.105
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bits<3> Rdn;
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bits<3> Rm;
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let Inst{5-3} = Rm;
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let Inst{2-0} = Rdn;
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}
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def tMUL : // A8.6.105 T1
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T1sItDPEncode<0b1101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
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IIC_iMUL32,
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"mul", "\t$Rdn, $Rm, $Rdn",
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[(set tGPR:$Rdn, (mul tGPR:$Rn, tGPR:$Rm))]>;
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// move inverse register
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def tMVN : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMVNr,
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@ -1043,16 +1017,11 @@ def tMVN : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMVNr,
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// Bitwise or register
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let isCommutable = 1 in
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def tORR : T1sIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iBITr,
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"orr", "\t$Rdn, $Rm",
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[(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>,
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T1DataProcessing<0b1100> {
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// A8.6.114
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bits<3> Rdn;
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bits<3> Rm;
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let Inst{5-3} = Rm;
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let Inst{2-0} = Rdn;
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}
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def tORR : // A8.6.114
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T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
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IIC_iBITr,
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"orr", "\t$Rdn, $Rm",
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[(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>;
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// Swaps
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def tREV : T1pI<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iUNAr,
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@ -1098,19 +1067,14 @@ def tREVSH : T1pI<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iUNAr,
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let Inst{2-0} = Rd;
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}
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// rotate right register
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def tROR : T1sIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iMOVsr,
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"ror", "\t$Rdn, $Rm",
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[(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>,
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T1DataProcessing<0b0111> {
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// A8.6.139
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bits<3> Rdn;
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bits<3> Rm;
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let Inst{5-3} = Rm;
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let Inst{2-0} = Rdn;
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}
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// Rotate right register
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def tROR : // A8.6.139
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T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
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IIC_iMOVsr,
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"ror", "\t$Rdn, $Rm",
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[(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>;
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// negate register
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// Negate register
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def tRSB : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iALUi,
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"rsb", "\t$Rd, $Rn, #0",
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[(set tGPR:$Rd, (ineg tGPR:$Rn))]>,
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@ -1124,16 +1088,11 @@ def tRSB : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iALUi,
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// Subtract with carry register
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let Uses = [CPSR] in
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def tSBC : T1sIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
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"sbc", "\t$Rdn, $Rm",
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[(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>,
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T1DataProcessing<0b0110> {
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// A8.6.151
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bits<3> Rdn;
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bits<3> Rm;
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let Inst{5-3} = Rm;
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let Inst{2-0} = Rdn;
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}
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def tSBC : // A8.6.151
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T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
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IIC_iALUr,
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"sbc", "\t$Rdn, $Rm",
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[(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>;
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// Subtract immediate
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def tSUBi3 : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, i32imm:$imm3), IIC_iALUi,
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@ -1149,16 +1108,11 @@ def tSUBi3 : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, i32imm:$imm3), IIC_iALUi,
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let Inst{2-0} = Rd;
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}
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def tSUBi8 : T1sIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8), IIC_iALUi,
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"sub", "\t$Rdn, $imm8",
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[(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>,
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T1General<{1,1,1,?,?}> {
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// A8.6.210 T2
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bits<3> Rdn;
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bits<8> imm8;
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let Inst{10-8} = Rdn;
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let Inst{7-0} = imm8;
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}
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def tSUBi8 : // A8.6.210 T2
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T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),
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IIC_iALUi,
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"sub", "\t$Rdn, $imm8",
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[(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>;
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// subtract register
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def tSUBrr : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
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