[Hexagon] Ignore indexed loads when handling unaligned loads

llvm-svn: 327037
This commit is contained in:
Krzysztof Parzyszek 2018-03-08 18:15:13 +00:00
parent c71c9aace8
commit 480ab2bbc4
2 changed files with 71 additions and 3 deletions

View File

@ -2540,9 +2540,6 @@ HexagonTargetLowering::LowerUnalignedLoad(SDValue Op, SelectionDAG &DAG)
unsigned NeedAlign = Subtarget.getTypeAlignment(LoadTy);
if (HaveAlign >= NeedAlign)
return Op;
// Indexed loads/stores are created after legalizing operations, so we
// shouldn't be getting unaligned post-incrementing loads at this point.
assert(LN->isUnindexed() && "Expecting only unindexed loads");
const SDLoc &dl(Op);
const DataLayout &DL = DAG.getDataLayout();
@ -2552,6 +2549,10 @@ HexagonTargetLowering::LowerUnalignedLoad(SDValue Op, SelectionDAG &DAG)
// If the load aligning is disabled or the load can be broken up into two
// smaller legal loads, do the default (target-independent) expansion.
bool DoDefault = false;
// Handle it in the default way if this is an indexed load.
if (!LN->isUnindexed())
DoDefault = true;
if (!AlignLoads) {
if (allowsMemoryAccess(Ctx, DL, LN->getMemoryVT(), AS, HaveAlign))
return Op;

View File

@ -0,0 +1,67 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; Check for successful compilation.
; CHECK: vmem
target triple = "hexagon"
; Function Attrs: nounwind
define dso_local void @f0(i8* %a0, i8* %a1) local_unnamed_addr #0 {
b0:
br label %b1
b1: ; preds = %b1, %b0
%v0 = phi i32 [ %v18, %b1 ], [ 0, %b0 ]
%v1 = getelementptr inbounds i8, i8* %a1, i32 %v0
%v2 = load <64 x i8>, <64 x i8>* undef, align 1, !tbaa !0, !alias.scope !3
%v3 = add <64 x i8> zeroinitializer, %v2
%v4 = getelementptr inbounds i8, i8* %a0, i32 undef
%v5 = getelementptr inbounds i8, i8* %a0, i32 undef
%v6 = getelementptr inbounds i8, i8* %a0, i32 undef
store i8 0, i8* undef, align 1, !tbaa !0, !alias.scope !6, !noalias !8
%v7 = extractelement <64 x i8> %v3, i32 12
store i8 %v7, i8* undef, align 1, !tbaa !0, !alias.scope !6, !noalias !8
store i8 0, i8* undef, align 1, !tbaa !0, !alias.scope !6, !noalias !8
store i8 undef, i8* %v4, align 1, !tbaa !0, !alias.scope !6, !noalias !8
store i8 0, i8* %v5, align 1, !tbaa !0, !alias.scope !6, !noalias !8
store i8 0, i8* undef, align 1, !tbaa !0, !alias.scope !6, !noalias !8
%v8 = extractelement <64 x i8> %v3, i32 36
store i8 %v8, i8* undef, align 1, !tbaa !0, !alias.scope !6, !noalias !8
store i8 0, i8* undef, align 1, !tbaa !0, !alias.scope !6, !noalias !8
%v9 = extractelement <64 x i8> %v3, i32 38
store i8 %v9, i8* undef, align 1, !tbaa !0, !alias.scope !6, !noalias !8
store i8 0, i8* undef, align 1, !tbaa !0, !alias.scope !6, !noalias !8
%v10 = extractelement <64 x i8> %v3, i32 41
store i8 %v10, i8* %v6, align 1, !tbaa !0, !alias.scope !6, !noalias !8
store i8 0, i8* undef, align 1, !tbaa !0, !alias.scope !6, !noalias !8
store i8 undef, i8* undef, align 1, !tbaa !0, !alias.scope !6, !noalias !8
%v11 = extractelement <64 x i8> %v3, i32 55
store i8 %v11, i8* undef, align 1, !tbaa !0, !alias.scope !6, !noalias !8
store i8 0, i8* undef, align 1, !tbaa !0, !alias.scope !6, !noalias !8
%v12 = extractelement <64 x i8> %v3, i32 58
store i8 %v12, i8* undef, align 1, !tbaa !0, !alias.scope !6, !noalias !8
store i8 0, i8* undef, align 1, !tbaa !0, !alias.scope !6, !noalias !8
%v13 = bitcast i8* %v1 to <64 x i8>*
%v14 = load <64 x i8>, <64 x i8>* %v13, align 1, !tbaa !0, !alias.scope !3
%v15 = add <64 x i8> zeroinitializer, %v14
%v16 = getelementptr inbounds i8, i8* %a0, i32 undef
%v17 = extractelement <64 x i8> %v15, i32 23
store i8 %v17, i8* %v16, align 1, !tbaa !0, !alias.scope !6, !noalias !8
%v18 = add i32 %v0, 64
br label %b1
}
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-length64b,+hvxv60" }
!0 = !{!1, !1, i64 0}
!1 = !{!"omnipotent char", !2, i64 0}
!2 = !{!"Simple C/C++ TBAA"}
!3 = !{!4}
!4 = distinct !{!4, !5}
!5 = distinct !{!5, !"LVerDomain"}
!6 = !{!7}
!7 = distinct !{!7, !5}
!8 = !{!4, !9, !10, !11}
!9 = distinct !{!9, !5}
!10 = distinct !{!10, !5}
!11 = distinct !{!11, !5}