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[AMDGPU][MC][DOC] Updated AMD GPU assembler description 

Stage 2: added detailed description of operands

See bug 36572: https://bugs.llvm.org/show_bug.cgi?id=36572

llvm-svn: 349368
This commit is contained in:
Dmitry Preobrazhensky 2018-12-17 17:38:11 +00:00
parent f700c8b253
commit 47eb63684d
279 changed files with 13099 additions and 5744 deletions
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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
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.. _amdgpu_synid7_addr_buf:
vaddr
===========================
This is an optional operand which may specify a 64-bit address, offset and/or index.
*Size:* 0, 1 or 2 dwords. Size is controlled by modifiers :ref:`addr64<amdgpu_synid_addr64>`, :ref:`offen<amdgpu_synid_offen>` and :ref:`idxen<amdgpu_synid_idxen>`:
* If only :ref:`addr64<amdgpu_synid_addr64>` is specified, this operand supplies a 64-bit address. Size is 2 dwords.
* If only :ref:`idxen<amdgpu_synid_idxen>` is specified, this operand supplies an index. Size is 1 dword.
* If only :ref:`offen<amdgpu_synid_offen>` is specified, this operand supplies an offset. Size is 1 dword.
* If both :ref:`idxen<amdgpu_synid_idxen>` and :ref:`offen<amdgpu_synid_offen>` are specified, index is in the first register and offset is in the second. Size is 2 dwords.
* If none of these modifiers are specified, this operand must be set to :ref:`off<amdgpu_synid_off>`.
* All other combinations of these modifiers are illegal.
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`off<amdgpu_synid_off>`

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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
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.. _amdgpu_synid7_addr_ds:
vaddr
===========================
An offset from the start of GDS/LDS memory.
*Size:* 1 dword.
*Operands:* :ref:`v<amdgpu_synid_v>`

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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_addr_flat:
vaddr
===========================
A 64-bit flat address.
*Size:* 2 dwords.
*Operands:* :ref:`v<amdgpu_synid_v>`

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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_addr_mimg:
vaddr
===========================
Image address which includes from one to four dimensional coordinates and other data used to locate a position in the image.
*Size:* 1, 2, 3, 4, 8 or 16 dwords. Actual size depends on opcode and specific image being handled.
Note 1. Image format and dimensions are encoded in the image resource constant but not in the instruction.
Note 2. Actually image address size may vary from 1 to 13 dwords, but assembler currently supports a limited range of register sequences.
*Operands:* :ref:`v<amdgpu_synid_v>`

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..
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* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_attr:
attr
===========================
Interpolation attribute and channel:
============== ===================================
Syntax Description
============== ===================================
attr{0..32}.x Attribute 0..32 with *x* channel.
attr{0..32}.y Attribute 0..32 with *y* channel.
attr{0..32}.z Attribute 0..32 with *z* channel.
attr{0..32}.w Attribute 0..32 with *w* channel.
============== ===================================
Examples:
.. code-block:: nasm
v_interp_p1_f32 v1, v0, attr0.x
v_interp_p1_f32 v1, v0, attr32.w

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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_base_smem_addr:
sbase
===========================
A 64-bit base address for scalar memory operations.
*Size:* 2 dwords.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`

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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_base_smem_buf:
sbase
===========================
A 128-bit buffer resource constant for scalar memory operations which provides a base address, a size and a stride.
*Size:* 4 dwords.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`

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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_bimm16:
imm16
===========================
An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 16 bits.

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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
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.. _amdgpu_synid7_bimm32:
imm32
===========================
An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 32 bits.

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..
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* *
* Automatically generated file, do not edit! *
* *
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.. _amdgpu_synid7_data_buf_atomic128:
vdata
===========================
Input data for an atomic instruction.
Optionally may serve as an output data:
* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
*Size:* 4 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
*Operands:* :ref:`v<amdgpu_synid_v>`

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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_data_buf_atomic32:
vdata
===========================
Input data for an atomic instruction.
Optionally may serve as an output data:
* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
*Size:* 1 dword by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
*Operands:* :ref:`v<amdgpu_synid_v>`

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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_data_buf_atomic64:
vdata
===========================
Input data for an atomic instruction.
Optionally may serve as an output data:
* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
*Size:* 2 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
*Operands:* :ref:`v<amdgpu_synid_v>`

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..
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* *
* Automatically generated file, do not edit! *
* *
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.. _amdgpu_synid7_data_mimg_atomic_cmp:
vdata
===========================
Input data for an atomic instruction.
Optionally may serve as an output data:
* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`tfe<amdgpu_synid_tfe>`:
* :ref:`dmask<amdgpu_synid_dmask>` may specify 2 data elements for 32-bit-per-pixel surfaces or 4 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
Note. The surface data format is indicated in the image resource constant but not in the instruction.
*Operands:* :ref:`v<amdgpu_synid_v>`

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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_data_mimg_atomic_reg:
vdata
===========================
Input data for an atomic instruction.
Optionally may serve as an output data:
* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`tfe<amdgpu_synid_tfe>`:
* :ref:`dmask<amdgpu_synid_dmask>` may specify 1 data element for 32-bit-per-pixel surfaces or 2 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
Note. The surface data format is indicated in the image resource constant but not in the instruction.
*Operands:* :ref:`v<amdgpu_synid_v>`

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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_data_mimg_store:
vdata
===========================
Image data to store by an *image_store* instruction.
*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` which may specify from 1 to 4 data elements. Each data element occupies 1 dword.
*Operands:* :ref:`v<amdgpu_synid_v>`

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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_dst_buf_128:
vdst
===========================
Instruction output: data read from a memory buffer.
*Size:* 4 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
*Operands:* :ref:`v<amdgpu_synid_v>`

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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_dst_buf_64:
vdst
===========================
Instruction output: data read from a memory buffer.
*Size:* 2 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
*Operands:* :ref:`v<amdgpu_synid_v>`

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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_dst_buf_96:
vdst
===========================
Instruction output: data read from a memory buffer.
*Size:* 3 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
*Operands:* :ref:`v<amdgpu_synid_v>`

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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_dst_buf_lds:
vdst
===========================
Instruction output: data read from a memory buffer.
If :ref:`lds<amdgpu_synid_lds>` is specified, this operand is ignored by H/W and data are stored directly into LDS.
*Size:* 1 dword by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
Note that :ref:`tfe<amdgpu_synid_tfe>` and :ref:`lds<amdgpu_synid_lds>` cannot be used together.
*Operands:* :ref:`v<amdgpu_synid_v>`

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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_dst_flat_atomic32:
vdst
===========================
Data returned by a 32-bit atomic flat instruction.
This is an optional operand. It must be used if and only if :ref:`glc<amdgpu_synid_glc>` is specified.
*Size:* 1 dword.
*Operands:* :ref:`v<amdgpu_synid_v>`

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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_dst_flat_atomic64:
vdst
===========================
Data returned by a 64-bit atomic flat instruction.
This is an optional operand. It must be used if and only if :ref:`glc<amdgpu_synid_glc>` is specified.
*Size:* 2 dwords.
*Operands:* :ref:`v<amdgpu_synid_v>`

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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_dst_mimg_gather4:
vdst
===========================
Image data to load by an *image_gather4* instruction.
*Size:* 4 data elements by default. Each data element occupies 1 dword. :ref:`tfe<amdgpu_synid_tfe>` adds one more dword if specified.
*Operands:* :ref:`v<amdgpu_synid_v>`

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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_dst_mimg_regular:
vdst
===========================
Image data to load by an image instruction.
*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`tfe<amdgpu_synid_tfe>`:
* :ref:`dmask<amdgpu_synid_dmask>` may specify from 1 to 4 data elements. Each data element occupies 1 dword.
* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
*Operands:* :ref:`v<amdgpu_synid_v>`

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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_fimm32:
imm32
===========================
An :ref:`integer_number<amdgpu_synid_integer_number>` or a :ref:`floating-point_number<amdgpu_synid_floating-point_number>`. The value is converted to *f32* as described :ref:`here<amdgpu_synid_lit_conv>`.

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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_hwreg:
hwreg
===========================
Bits of a hardware register being accessed.
The bits of this operand have the following meaning:
============ ===================================
Bits Description
============ ===================================
5:0 Register *id*.
10:6 First bit *offset* (0..31).
15:11 *Size* in bits (1..32).
============ ===================================
This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` or using the syntax described below.
==================================== ============================================================================
Syntax Description
==================================== ============================================================================
hwreg({0..63}) All bits of a register indicated by its *id*.
hwreg(<*name*>) All bits of a register indicated by its *name*.
hwreg({0..63}, {0..31}, {1..32}) Register bits indicated by register *id*, first bit *offset* and *size*.
hwreg(<*name*>, {0..31}, {1..32}) Register bits indicated by register *name*, first bit *offset* and *size*.
==================================== ============================================================================
Register *id*, *offset* and *size* must be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`.
Defined register *names* include:
=================== ==========================================
Name Description
=================== ==========================================
HW_REG_MODE Shader writeable mode bits.
HW_REG_STATUS Shader read-only status.
HW_REG_TRAPSTS Trap status.
HW_REG_HW_ID Id of wave, simd, compute unit, etc.
HW_REG_GPR_ALLOC Per-wave SGPR and VGPR allocation.
HW_REG_LDS_ALLOC Per-wave LDS allocation.
HW_REG_IB_STS Counters of outstanding instructions.
=================== ==========================================
Examples:
.. code-block:: nasm
s_getreg_b32 s2, 0x6
s_getreg_b32 s2, hwreg(15)
s_getreg_b32 s2, hwreg(51, 1, 31)
s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1)

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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_label:
label
===========================
A branch target which is a 16-bit signed integer treated as a PC-relative dword offset.
This operand may be specified as:
* An :ref:`integer_number<amdgpu_synid_integer_number>`. The number is truncated to 16 bits.
* An :ref:`absolute_expression<amdgpu_synid_absolute_expression>` which must start with an :ref:`integer_number<amdgpu_synid_integer_number>`. The value of the expression is truncated to 16 bits.
* A :ref:`symbol<amdgpu_synid_symbol>` (for example, a label). The value is handled as a 16-bit PC-relative dword offset to be resolved by a linker.
Examples:
.. code-block:: nasm
offset = 30
s_branch loop_end
s_branch 2 + offset
s_branch 32
loop_end:

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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_mod:
m
===========================
This operand may be used with floating point operand modifiers :ref:`abs<amdgpu_synid_abs>` and :ref:`neg<amdgpu_synid_neg>`.

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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_msg:
msg
===========================
A 16-bit message code. The bits of this operand have the following meaning:
============ ======================================================
Bits Description
============ ======================================================
3:0 Message *type*.
6:4 Optional *operation*.
9:7 Optional *parameters*.
15:10 Unused.
============ ======================================================
This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` or using the syntax described below:
======================================== ========================================================================
Syntax Description
======================================== ========================================================================
sendmsg(<*type*>) A message identified by its *type*.
sendmsg(<*type*>, <*op*>) A message identified by its *type* and *operation*.
sendmsg(<*type*>, <*op*>, <*stream*>) A message identified by its *type* and *operation* with a stream *id*.
======================================== ========================================================================
*Type* may be specified using message *name* or message *id*.
*Op* may be specified using operation *name* or operation *id*.
Stream *id* is an integer in the range 0..3.
Message *id*, operation *id* and stream *id* must be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`.
Each message type supports specific operations:
================= ========== ============================== ============ ==========
Message name Message Id Supported Operations Operation Id Stream Id
================= ========== ============================== ============ ==========
MSG_INTERRUPT 1 \- \- \-
MSG_GS 2 GS_OP_CUT 1 Optional
\ GS_OP_EMIT 2 Optional
\ GS_OP_EMIT_CUT 3 Optional
MSG_GS_DONE 3 GS_OP_NOP 0 \-
\ GS_OP_CUT 1 Optional
\ GS_OP_EMIT 2 Optional
\ GS_OP_EMIT_CUT 3 Optional
MSG_SYSMSG 15 SYSMSG_OP_ECC_ERR_INTERRUPT 1 \-
\ SYSMSG_OP_REG_RD 2 \-
\ SYSMSG_OP_HOST_TRAP_ACK 3 \-
\ SYSMSG_OP_TTRACE_PC 4 \-
================= ========== ============================== ============ ==========
Examples:
.. code-block:: nasm
s_sendmsg 0x12
s_sendmsg sendmsg(MSG_INTERRUPT)
s_sendmsg sendmsg(2, GS_OP_CUT)
s_sendmsg sendmsg(MSG_GS, GS_OP_EMIT)
s_sendmsg sendmsg(MSG_GS, 2)
s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_EMIT_CUT, 1)
s_sendmsg sendmsg(MSG_SYSMSG, SYSMSG_OP_TTRACE_PC)

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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_offset_buf:
soffset
===========================
An unsigned byte offset.
*Size:* 1 dword.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`

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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_offset_smem:
soffset
===========================
An unsigned offset added to the base address to get memory address.
* If offset is specified as a register, it supplies an unsigned byte offset but 2 lsb's are ignored.
* If offset is specified as an :ref:`uimm32<amdgpu_synid_uimm32>`, it supplies a 32-bit unsigned byte offset but 2 lsb's are ignored.
* If offset is specified as an :ref:`uimm8<amdgpu_synid_uimm8>`, it supplies an 8-bit unsigned dword offset.
*Size:* 1 dword.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`uimm8<amdgpu_synid_uimm8>`, :ref:`uimm32<amdgpu_synid_uimm32>`

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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_opt:
opt
===========================
This is an optional operand. It must be used if and only if :ref:`glc<amdgpu_synid_glc>` is specified.

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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_param:
param
===========================
Interpolation parameter to read:
============ ===================================
Syntax Description
============ ===================================
p0 Parameter *P0*.
p10 Parameter *P10*.
p20 Parameter *P20*.
============ ===================================

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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_ret:
dst
===========================
This is an input operand. It may optionally serve as a destination if :ref:`glc<amdgpu_synid_glc>` is specified.

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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_rsrc_buf:
srsrc
===========================
Buffer resource constant which defines the address and characteristics of the buffer in memory.
*Size:* 4 dwords.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`

17
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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_rsrc_mimg:
srsrc
===========================
Image resource constant which defines the location of the image buffer in memory, its dimensions, tiling, and data format.
*Size:* 8 dwords by default, 4 dwords if :ref:`r128<amdgpu_synid_r128>` is specified.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`

17
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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_samp_mimg:
ssamp
===========================
Sampler constant used to specify filtering options applied to the image data after it is read.
*Size:* 4 dwords.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`

17
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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_sdst128_0:
sdst
===========================
Instruction output.
*Size:* 4 dwords.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`

17
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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_sdst256_0:
sdst
===========================
Instruction output.
*Size:* 8 dwords.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`

17
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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_sdst32_0:
sdst
===========================
Instruction output.
*Size:* 1 dword.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`

17
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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_sdst32_1:
sdst
===========================
Instruction output.
*Size:* 1 dword.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`

17
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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_sdst32_2:
sdst
===========================
Instruction output.
*Size:* 1 dword.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`trap<amdgpu_synid_trap>`

17
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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_sdst512_0:
sdst
===========================
Instruction output.
*Size:* 16 dwords.
*Operands:* :ref:`s<amdgpu_synid_s>`

17
llvm/docs/AMDGPU/gfx7_sdst64_0.rst Normal file
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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_sdst64_0:
sdst
===========================
Instruction output.
*Size:* 2 dwords.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`

17
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@ -0,0 +1,17 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_sdst64_1:
sdst
===========================
Instruction output.
*Size:* 2 dwords.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`

14
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@ -0,0 +1,14 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_simm16:
imm16
===========================
An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 16 bits and then sign-extended to 32 bits.

17
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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_src32_0:
src
===========================
Instruction input.
*Size:* 1 dword.
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`

17
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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_src32_1:
src
===========================
Instruction input.
*Size:* 1 dword.
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`iconst<amdgpu_synid_iconst>`

17
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@ -0,0 +1,17 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_src32_2:
src
===========================
Instruction input.
*Size:* 1 dword.
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`

17
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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_src32_3:
src
===========================
Instruction input.
*Size:* 1 dword.
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`

17
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@ -0,0 +1,17 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_src64_0:
src
===========================
Instruction input.
*Size:* 2 dwords.
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`

17
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@ -0,0 +1,17 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_src64_1:
src
===========================
Instruction input.
*Size:* 2 dwords.
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`

17
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@ -0,0 +1,17 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_src64_2:
src
===========================
Instruction input.
*Size:* 2 dwords.
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`iconst<amdgpu_synid_iconst>`

28
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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_src_exp:
vsrc
===========================
Data to copy to export buffers. This is an optional operand. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
:ref:`compr<amdgpu_synid_compr>` modifier indicates use of compressed (16-bit) data. This limits number of source operands from 4 to 2:
* src0 and src1 must specify the first register (or :ref:`off<amdgpu_synid_off>`).
* src2 and src3 must specify the second register (or :ref:`off<amdgpu_synid_off>`).
An example:
.. code-block:: nasm
exp mrtz v3, v3, off, off compr
*Size:* 1 dword.
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`off<amdgpu_synid_off>`

17
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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_ssrc32_0:
ssrc
===========================
Instruction input.
*Size:* 1 dword.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`

17
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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_ssrc32_1:
ssrc
===========================
Instruction input.
*Size:* 1 dword.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`

17
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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_ssrc32_2:
ssrc
===========================
Instruction input.
*Size:* 1 dword.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`

17
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@ -0,0 +1,17 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_ssrc32_3:
ssrc
===========================
Instruction input.
*Size:* 1 dword.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`iconst<amdgpu_synid_iconst>`, :ref:`literal<amdgpu_synid_literal>`

17
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@ -0,0 +1,17 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_ssrc32_4:
ssrc
===========================
Instruction input.
*Size:* 1 dword.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`iconst<amdgpu_synid_iconst>`

17
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@ -0,0 +1,17 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_ssrc64_0:
ssrc
===========================
Instruction input.
*Size:* 2 dwords.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`

17
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@ -0,0 +1,17 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_ssrc64_1:
ssrc
===========================
Instruction input.
*Size:* 2 dwords.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`

17
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@ -0,0 +1,17 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_ssrc64_2:
ssrc
===========================
Instruction input.
*Size:* 2 dwords.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`

17
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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_ssrc64_3:
ssrc
===========================
Instruction input.
*Size:* 2 dwords.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`

24
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@ -0,0 +1,24 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_tgt:
tgt
===========================
An export target:
============== ===================================
Syntax Description
============== ===================================
pos{0..3} Copy vertex position 0..3.
param{0..31} Copy vertex parameter 0..31.
mrt{0..7} Copy pixel color to the MRTs 0..7.
mrtz Copy pixel depth (Z) data.
null Copy nothing.
============== ===================================

14
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@ -0,0 +1,14 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_type_dev:
Type deviation
===========================
*Type* of this operand differs from *type* :ref:`implied by the opcode<amdgpu_syn_instruction_type>`. This tag specifies actual operand *type*.

14
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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_uimm16:
imm16
===========================
An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 16 bits and then zero-extended to 32 bits.

17
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@ -0,0 +1,17 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_vcc_64:
vcc
===========================
Vector condition code.
*Size:* 2 dwords.
*Operands:* :ref:`vcc<amdgpu_synid_vcc>`

17
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@ -0,0 +1,17 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_vdata128_0:
vdata
===========================
Instruction input.
*Size:* 4 dwords.
*Operands:* :ref:`v<amdgpu_synid_v>`

17
llvm/docs/AMDGPU/gfx7_vdata32_0.rst Normal file
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@ -0,0 +1,17 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_vdata32_0:
vdata
===========================
Instruction input.
*Size:* 1 dword.
*Operands:* :ref:`v<amdgpu_synid_v>`

17
llvm/docs/AMDGPU/gfx7_vdata64_0.rst Normal file
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@ -0,0 +1,17 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_vdata64_0:
vdata
===========================
Instruction input.
*Size:* 2 dwords.
*Operands:* :ref:`v<amdgpu_synid_v>`

17
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@ -0,0 +1,17 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_vdata96_0:
vdata
===========================
Instruction input.
*Size:* 3 dwords.
*Operands:* :ref:`v<amdgpu_synid_v>`

17
llvm/docs/AMDGPU/gfx7_vdst128_0.rst Normal file
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@ -0,0 +1,17 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_vdst128_0:
vdst
===========================
Instruction output.
*Size:* 4 dwords.
*Operands:* :ref:`v<amdgpu_synid_v>`

17
llvm/docs/AMDGPU/gfx7_vdst32_0.rst Normal file
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@ -0,0 +1,17 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_vdst32_0:
vdst
===========================
Instruction output.
*Size:* 1 dword.
*Operands:* :ref:`v<amdgpu_synid_v>`

17
llvm/docs/AMDGPU/gfx7_vdst64_0.rst Normal file
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@ -0,0 +1,17 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_vdst64_0:
vdst
===========================
Instruction output.
*Size:* 2 dwords.
*Operands:* :ref:`v<amdgpu_synid_v>`

17
llvm/docs/AMDGPU/gfx7_vdst96_0.rst Normal file
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@ -0,0 +1,17 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_vdst96_0:
vdst
===========================
Instruction output.
*Size:* 3 dwords.
*Operands:* :ref:`v<amdgpu_synid_v>`

17
llvm/docs/AMDGPU/gfx7_vsrc128_0.rst Normal file
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@ -0,0 +1,17 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_vsrc128_0:
vsrc
===========================
Instruction input.
*Size:* 4 dwords.
*Operands:* :ref:`v<amdgpu_synid_v>`

17
llvm/docs/AMDGPU/gfx7_vsrc32_0.rst Normal file
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@ -0,0 +1,17 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_vsrc32_0:
vsrc
===========================
Instruction input.
*Size:* 1 dword.
*Operands:* :ref:`v<amdgpu_synid_v>`

17
llvm/docs/AMDGPU/gfx7_vsrc64_0.rst Normal file
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@ -0,0 +1,17 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_vsrc64_0:
vsrc
===========================
Instruction input.
*Size:* 2 dwords.
*Operands:* :ref:`v<amdgpu_synid_v>`

55
llvm/docs/AMDGPU/gfx7_waitcnt.rst Normal file
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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid7_waitcnt:
waitcnt
===========================
Counts of outstanding instructions to wait for.
The bits of this operand have the following meaning:
============ ======================================================
Bits Description
============ ======================================================
3:0 VM_CNT: vector memory operations count.
6:4 EXP_CNT: export count.
12:8 LGKM_CNT: LDS, GDS, Constant and Message count.
============ ======================================================
This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_synid_integer_number>`
or as a combination of the following symbolic helpers:
====================== ======================================================================
Syntax Description
====================== ======================================================================
vmcnt(<*N*>) VM_CNT value. *N* must not exceed the largest VM_CNT value.
expcnt(<*N*>) EXP_CNT value. *N* must not exceed the largest EXP_CNT value.
lgkmcnt(<*N*>) LGKM_CNT value. *N* must not exceed the largest LGKM_CNT value.
vmcnt_sat(<*N*>) VM_CNT value computed as min(*N*, the largest VM_CNT value).
expcnt_sat(<*N*>) EXP_CNT value computed as min(*N*, the largest EXP_CNT value).
lgkmcnt_sat(<*N*>) LGKM_CNT value computed as min(*N*, the largest LGKM_CNT value).
====================== ======================================================================
These helpers may be specified in any order. Ampersands and commas may be used as optional separators.
*N* is either an
:ref:`integer number<amdgpu_synid_integer_number>` or an
:ref:`absolute expression<amdgpu_synid_absolute_expression>`.
Examples:
.. code-block:: nasm
s_waitcnt 0
s_waitcnt vmcnt(1)
s_waitcnt expcnt(2) lgkmcnt(3)
s_waitcnt vmcnt(1) expcnt(2) lgkmcnt(3)
s_waitcnt vmcnt(1), expcnt(2), lgkmcnt(3)
s_waitcnt vmcnt(1) & lgkmcnt_sat(100) & expcnt(2)

22
llvm/docs/AMDGPU/gfx8_addr_buf.rst Normal file
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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid8_addr_buf:
vaddr
===========================
This is an optional operand which may specify offset and/or index.
*Size:* 0, 1 or 2 dwords. Size is controlled by modifiers :ref:`offen<amdgpu_synid_offen>` and :ref:`idxen<amdgpu_synid_idxen>`:
* If only :ref:`idxen<amdgpu_synid_idxen>` is specified, this operand supplies an index. Size is 1 dword.
* If only :ref:`offen<amdgpu_synid_offen>` is specified, this operand supplies an offset. Size is 1 dword.
* If both modifiers are specified, index is in the first register and offset is in the second. Size is 2 dwords.
* If none of these modifiers are specified, this operand must be set to :ref:`off<amdgpu_synid_off>`.
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`off<amdgpu_synid_off>`

17
llvm/docs/AMDGPU/gfx8_addr_ds.rst Normal file
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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid8_addr_ds:
vaddr
===========================
An offset from the start of GDS/LDS memory.
*Size:* 1 dword.
*Operands:* :ref:`v<amdgpu_synid_v>`

17
llvm/docs/AMDGPU/gfx8_addr_flat.rst Normal file
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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid8_addr_flat:
vaddr
===========================
A 64-bit flat address.
*Size:* 2 dwords.
*Operands:* :ref:`v<amdgpu_synid_v>`

21
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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid8_addr_mimg:
vaddr
===========================
Image address which includes from one to four dimensional coordinates and other data used to locate a position in the image.
*Size:* 1, 2, 3, 4, 8 or 16 dwords. Actual size depends on opcode and specific image being handled.
Note 1. Image format and dimensions are encoded in the image resource constant but not in the instruction.
Note 2. Actually image address size may vary from 1 to 13 dwords, but assembler currently supports a limited range of register sequences.
*Operands:* :ref:`v<amdgpu_synid_v>`

30
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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid8_attr:
attr
===========================
Interpolation attribute and channel:
============== ===================================
Syntax Description
============== ===================================
attr{0..32}.x Attribute 0..32 with *x* channel.
attr{0..32}.y Attribute 0..32 with *y* channel.
attr{0..32}.z Attribute 0..32 with *z* channel.
attr{0..32}.w Attribute 0..32 with *w* channel.
============== ===================================
Examples:
.. code-block:: nasm
v_interp_p1_f32 v1, v0, attr0.x
v_interp_p1_f32 v1, v0, attr32.w

17
llvm/docs/AMDGPU/gfx8_base_smem_addr.rst Normal file
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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid8_base_smem_addr:
sbase
===========================
A 64-bit base address for scalar memory operations.
*Size:* 2 dwords.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`

17
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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid8_base_smem_buf:
sbase
===========================
A 128-bit buffer resource constant for scalar memory operations which provides a base address, a size and a stride.
*Size:* 4 dwords.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`

14
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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid8_bimm16:
imm16
===========================
An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 16 bits.

14
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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid8_bimm32:
imm32
===========================
An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 32 bits.

21
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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid8_data_buf_atomic128:
vdata
===========================
Input data for an atomic instruction.
Optionally may serve as an output data:
* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
*Size:* 4 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
*Operands:* :ref:`v<amdgpu_synid_v>`

21
llvm/docs/AMDGPU/gfx8_data_buf_atomic32.rst Normal file
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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid8_data_buf_atomic32:
vdata
===========================
Input data for an atomic instruction.
Optionally may serve as an output data:
* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
*Size:* 1 dword by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
*Operands:* :ref:`v<amdgpu_synid_v>`

21
llvm/docs/AMDGPU/gfx8_data_buf_atomic64.rst Normal file
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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid8_data_buf_atomic64:
vdata
===========================
Input data for an atomic instruction.
Optionally may serve as an output data:
* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
*Size:* 2 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
*Operands:* :ref:`v<amdgpu_synid_v>`

20
llvm/docs/AMDGPU/gfx8_data_buf_d16_128.rst Normal file
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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid8_data_buf_d16_128:
vdata
===========================
16-bit data to store by a buffer instruction.
*Size:* depends on GFX8 GPU revision:
* 4 dwords for GFX8.0. This H/W supports no packing.
* 2 dwords for GFX8.1+. This H/W supports data packing.
*Operands:* :ref:`v<amdgpu_synid_v>`

17
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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid8_data_buf_d16_32:
vdata
===========================
16-bit data to store by a buffer instruction.
*Size:* 1 dword.
*Operands:* :ref:`v<amdgpu_synid_v>`

20
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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid8_data_buf_d16_64:
vdata
===========================
16-bit data to store by a buffer instruction.
*Size:* depends on GFX8 GPU revision:
* 2 dwords for GFX8.0. This H/W supports no packing.
* 1 dword for GFX8.1+. This H/W supports data packing.
*Operands:* :ref:`v<amdgpu_synid_v>`

20
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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid8_data_buf_d16_96:
vdata
===========================
16-bit data to store by a buffer instruction.
*Size:* depends on GFX8 GPU revision:
* 3 dwords for GFX8.0. This H/W supports no packing.
* 2 dwords for GFX8.1+. This H/W supports data packing.
*Operands:* :ref:`v<amdgpu_synid_v>`

27
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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid8_data_mimg_atomic_cmp:
vdata
===========================
Input data for an atomic instruction.
Optionally may serve as an output data:
* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`tfe<amdgpu_synid_tfe>`:
* :ref:`dmask<amdgpu_synid_dmask>` may specify 2 data elements for 32-bit-per-pixel surfaces or 4 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
Note. The surface data format is indicated in the image resource constant but not in the instruction.
*Operands:* :ref:`v<amdgpu_synid_v>`

26
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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid8_data_mimg_atomic_reg:
vdata
===========================
Input data for an atomic instruction.
Optionally may serve as an output data:
* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`tfe<amdgpu_synid_tfe>`:
* :ref:`dmask<amdgpu_synid_dmask>` may specify 1 data element for 32-bit-per-pixel surfaces or 2 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
Note. The surface data format is indicated in the image resource constant but not in the instruction.
*Operands:* :ref:`v<amdgpu_synid_v>`

18
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..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid8_data_mimg_store:
vdata
===========================
Image data to store by an *image_store* instruction.
*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` which may specify from 1 to 4 data elements. Each data element occupies 1 dword.
*Operands:* :ref:`v<amdgpu_synid_v>`

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