Teach DAGCombiner how to fold a SIGN_EXTEND_INREG of a BUILD_VECTOR of
ConstantSDNodes (or UNDEFs) into a simple BUILD_VECTOR. For example, given the following sequence of dag nodes: i32 C = Constant<1> v4i32 V = BUILD_VECTOR C, C, C, C v4i32 Result = SIGN_EXTEND_INREG V, ValueType:v4i1 The SIGN_EXTEND_INREG node can be folded into a build_vector since the vector in input is a BUILD_VECTOR of constants. The optimized sequence is: i32 C = Constant<-1> v4i32 Result = BUILD_VECTOR C, C, C, C llvm-svn: 198084
This commit is contained in:
Andrea Di Biagio
parent
ba2f146c87
commit
46dcddb350
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@ -70,6 +70,10 @@ namespace ISD {
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/// BUILD_VECTOR where all of the elements are 0 or undef.
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bool isBuildVectorAllZeros(const SDNode *N);
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/// \brief Return true if the specified node is a BUILD_VECTOR node of
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/// all ConstantSDNode or undef.
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bool isBuildVectorOfConstantSDNodes(const SDNode *N);
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/// isScalarToVector - Return true if the specified node is a
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/// ISD::SCALAR_TO_VECTOR node or a BUILD_VECTOR node where only the low
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/// element is not an undef.
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@ -5511,6 +5511,29 @@ SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
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BSwap, N1);
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}
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// Fold a sext_inreg of a build_vector of ConstantSDNodes or undefs
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// into a build_vector.
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if (ISD::isBuildVectorOfConstantSDNodes(N0.getNode())) {
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SmallVector<SDValue, 8> Elts;
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unsigned NumElts = N0->getNumOperands();
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unsigned ShAmt = VTBits - EVTBits;
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for (unsigned i = 0; i != NumElts; ++i) {
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SDValue Op = N0->getOperand(i);
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if (Op->getOpcode() == ISD::UNDEF) {
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Elts.push_back(Op);
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continue;
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}
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ConstantSDNode *CurrentND = cast<ConstantSDNode>(Op);
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const APInt &C = CurrentND->getAPIntValue();
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Elts.push_back(DAG.getConstant(C.shl(ShAmt).ashr(ShAmt),
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Op.getValueType()));
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}
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return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, &Elts[0], NumElts);
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}
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return SDValue();
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}
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@ -179,6 +179,22 @@ bool ISD::isBuildVectorAllZeros(const SDNode *N) {
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return true;
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}
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/// \brief Return true if the specified node is a BUILD_VECTOR node of
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/// all ConstantSDNode or undef.
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bool ISD::isBuildVectorOfConstantSDNodes(const SDNode *N) {
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if (N->getOpcode() != ISD::BUILD_VECTOR)
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return false;
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for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
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SDValue Op = N->getOperand(i);
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if (Op.getOpcode() == ISD::UNDEF)
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continue;
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if (!isa<ConstantSDNode>(Op))
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return false;
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}
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return true;
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}
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/// isScalarToVector - Return true if the specified node is a
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/// ISD::SCALAR_TO_VECTOR node or a BUILD_VECTOR node where only the low
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/// element is not an undef.
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@ -3,10 +3,20 @@
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
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target triple = "x86_64-apple-darwin11.2.0"
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; CHECK: @foo8
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; CHECK: psll
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; CHECK: psraw
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; CHECK: pblendvb
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; During legalization, the vselect mask is 'type legalized' into a
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; wider BUILD_VECTOR. This causes the introduction of a new
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; sign_extend_inreg in the DAG.
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;
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; A sign_extend_inreg of a vector of ConstantSDNode or undef can be
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; always folded into a simple build_vector.
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;
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; Make sure that the sign_extend_inreg is simplified and that we
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; don't generate psll, psraw and pblendvb from the vselect.
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; CHECK-LABEL: foo8
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; CHECK-NOT: psll
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; CHECK-NOT: psraw
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; CHECK-NOT: pblendvb
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; CHECK: ret
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define void @foo8(float* nocapture %RET) nounwind {
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allocas:
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@ -17,4 +27,3 @@ allocas:
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ret void
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}
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@ -5,7 +5,7 @@
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; shifting the needed bit to the MSB, and not using shl+sra.
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;CHECK-LABEL: vsel_float:
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;CHECK: movl $-2147483648
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;CHECK: movl $-1
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;CHECK-NEXT: movd
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;CHECK-NEXT: blendvps
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;CHECK: ret
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@ -15,7 +15,7 @@ define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) {
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}
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;CHECK-LABEL: vsel_4xi8:
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;CHECK: movl $-2147483648
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;CHECK: movl $-1
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;CHECK-NEXT: movd
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;CHECK-NEXT: blendvps
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;CHECK: ret
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@ -26,12 +26,12 @@ define <4 x i8> @vsel_4xi8(<4 x i8> %v1, <4 x i8> %v2) {
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; We do not have native support for v8i16 blends and we have to use the
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; blendvb instruction or a sequence of NAND/OR/AND. Make sure that we do not r
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; blendvb instruction or a sequence of NAND/OR/AND. Make sure that we do not
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; reduce the mask in this case.
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;CHECK-LABEL: vsel_8xi16:
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;CHECK: psllw
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;CHECK: psraw
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;CHECK: pblendvb
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;CHECK: andps
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;CHECK: andps
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;CHECK: orps
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;CHECK: ret
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define <8 x i16> @vsel_8xi16(<8 x i16> %v1, <8 x i16> %v2) {
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%vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x i16> %v1, <8 x i16> %v2
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@ -1,9 +1,9 @@
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; RUN: llc < %s -march=x86 -mcpu=yonah -mattr=+sse2,-sse4.1 | FileCheck %s
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; CHECK: vsel_float
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; CHECK: pandn
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; CHECK: pand
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; CHECK: por
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; CHECK: xorps
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; CHECK: movss
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; CHECK: orps
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; CHECK: ret
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define void@vsel_float(<4 x float>* %v1, <4 x float>* %v2) {
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%A = load <4 x float>* %v1
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@ -14,9 +14,9 @@ define void@vsel_float(<4 x float>* %v1, <4 x float>* %v2) {
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}
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; CHECK: vsel_i32
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; CHECK: pandn
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; CHECK: pand
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; CHECK: por
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; CHECK: xorps
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; CHECK: movss
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; CHECK: orps
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; CHECK: ret
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define void@vsel_i32(<4 x i32>* %v1, <4 x i32>* %v2) {
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%A = load <4 x i32>* %v1
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@ -0,0 +1,133 @@
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; RUN: llc -march=x86-64 -mcpu=corei7 -mattr=-sse4.1 < %s | FileCheck %s
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; Verify that we don't emit packed vector shifts instructions if the
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; condition used by the vector select is a vector of constants.
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define <4 x float> @test1(<4 x float> %a, <4 x float> %b) {
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%1 = select <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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; CHECK-LABEL: test1
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: ret
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define <4 x float> @test2(<4 x float> %a, <4 x float> %b) {
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%1 = select <4 x i1> <i1 true, i1 true, i1 false, i1 false>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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; CHECK-LABEL: test2
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: ret
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define <4 x float> @test3(<4 x float> %a, <4 x float> %b) {
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%1 = select <4 x i1> <i1 false, i1 false, i1 true, i1 true>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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; CHECK-LABEL: test3
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: ret
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define <4 x float> @test4(<4 x float> %a, <4 x float> %b) {
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%1 = select <4 x i1> <i1 false, i1 false, i1 false, i1 false>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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; CHECK-LABEL: test4
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: movaps %xmm1, %xmm0
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; CHECK: ret
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define <4 x float> @test5(<4 x float> %a, <4 x float> %b) {
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%1 = select <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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; CHECK-LABEL: test5
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: ret
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define <8 x i16> @test6(<8 x i16> %a, <8 x i16> %b) {
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%1 = select <8 x i1> <i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false>, <8 x i16> %a, <8 x i16> %a
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test6
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: ret
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define <8 x i16> @test7(<8 x i16> %a, <8 x i16> %b) {
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%1 = select <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test7
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: ret
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define <8 x i16> @test8(<8 x i16> %a, <8 x i16> %b) {
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%1 = select <8 x i1> <i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test8
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: ret
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define <8 x i16> @test9(<8 x i16> %a, <8 x i16> %b) {
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%1 = select <8 x i1> <i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test9
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: movaps %xmm1, %xmm0
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; CHECK-NEXT: ret
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define <8 x i16> @test10(<8 x i16> %a, <8 x i16> %b) {
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%1 = select <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test10
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: ret
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define <8 x i16> @test11(<8 x i16> %a, <8 x i16> %b) {
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%1 = select <8 x i1> <i1 false, i1 true, i1 true, i1 false, i1 undef, i1 true, i1 true, i1 undef>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test11
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: ret
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define <8 x i16> @test12(<8 x i16> %a, <8 x i16> %b) {
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%1 = select <8 x i1> <i1 false, i1 false, i1 undef, i1 false, i1 false, i1 false, i1 false, i1 undef>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test12
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: ret
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define <8 x i16> @test13(<8 x i16> %a, <8 x i16> %b) {
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%1 = select <8 x i1> <i1 undef, i1 undef, i1 undef, i1 undef, i1 undef, i1 undef, i1 undef, i1 undef>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test13
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: ret
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