Added for disassembly the following instructions:
o Store Return State (SRSW, SRS) o Load/Store Coprocessor (LDC/STC and friends) o MSR (immediate) llvm-svn: 96380
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@ -933,12 +933,27 @@ def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
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let Inst{7-4} = 0b0010;
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let Inst{7-4} = 0b0010;
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}
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}
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// Supervisor call (software interrupt) -- for disassembly only
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// Supervisor Call (Software Interrupt) -- for disassembly only
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let isCall = 1 in {
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let isCall = 1 in {
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def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
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def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
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[/* For disassembly only; pattern left blank */]>;
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[/* For disassembly only; pattern left blank */]>;
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}
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}
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// Store Return State -- for disassembly only
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def SRSW : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, i32imm:$opt),
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NoItinerary, "srs${addr:submode}\tsp!, $opt",
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[/* For disassembly only; pattern left blank */]> {
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let Inst{31-28} = 0b1111;
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let Inst{22-20} = 0b110; // W = 1
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}
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def SRS : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, i32imm:$mode),
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NoItinerary, "srs${addr:submode}\tsp, $mode",
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[/* For disassembly only; pattern left blank */]> {
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let Inst{31-28} = 0b1111;
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let Inst{22-20} = 0b100; // W = 0
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}
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Load / store Instructions.
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// Load / store Instructions.
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//
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//
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@ -2203,6 +2218,102 @@ def CDP2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
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let Inst{4} = 0;
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let Inst{4} = 0;
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}
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}
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class ACI<dag oops, dag iops, string opc, string asm>
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: I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, NoItinerary,
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opc, asm, "", [/* For disassembly only; pattern left blank */]> {
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let Inst{27-25} = 0b110;
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}
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multiclass LdStCop<bits<4> op31_28, bit load, string opc> {
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def _OFFSET : ACI<(outs),
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(ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
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opc, "\tp$cop, cr$CRd, $addr"> {
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let Inst{31-28} = op31_28;
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let Inst{24} = 1; // P = 1
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let Inst{21} = 0; // W = 0
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let Inst{22} = 0; // D = 0
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let Inst{20} = load;
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}
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def _PRE : ACI<(outs),
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(ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
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opc, "\tp$cop, cr$CRd, $addr!"> {
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let Inst{31-28} = op31_28;
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let Inst{24} = 1; // P = 1
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let Inst{21} = 1; // W = 1
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let Inst{22} = 0; // D = 0
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let Inst{20} = load;
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}
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def _POST : ACI<(outs),
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(ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
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opc, "\tp$cop, cr$CRd, [$base], $offset"> {
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let Inst{31-28} = op31_28;
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let Inst{24} = 0; // P = 0
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let Inst{21} = 1; // W = 1
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let Inst{22} = 0; // D = 0
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let Inst{20} = load;
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}
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def _OPTION : ACI<(outs),
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(ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, i32imm:$option),
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opc, "\tp$cop, cr$CRd, [$base], $option"> {
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let Inst{31-28} = op31_28;
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let Inst{24} = 0; // P = 0
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let Inst{23} = 1; // U = 1
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let Inst{21} = 0; // W = 0
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let Inst{22} = 0; // D = 0
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let Inst{20} = load;
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}
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def L_OFFSET : ACI<(outs),
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(ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
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opc, "l\tp$cop, cr$CRd, $addr"> {
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let Inst{31-28} = op31_28;
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let Inst{24} = 1; // P = 1
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let Inst{21} = 0; // W = 0
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let Inst{22} = 1; // D = 1
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let Inst{20} = load;
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}
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def L_PRE : ACI<(outs),
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(ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
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opc, "l\tp$cop, cr$CRd, $addr!"> {
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let Inst{31-28} = op31_28;
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let Inst{24} = 1; // P = 1
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let Inst{21} = 1; // W = 1
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let Inst{22} = 1; // D = 1
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let Inst{20} = load;
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}
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def L_POST : ACI<(outs),
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(ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
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opc, "l\tp$cop, cr$CRd, [$base], $offset"> {
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let Inst{31-28} = op31_28;
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let Inst{24} = 0; // P = 0
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let Inst{21} = 1; // W = 1
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let Inst{22} = 1; // D = 1
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let Inst{20} = load;
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}
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def L_OPTION : ACI<(outs),
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(ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, nohash_imm:$option),
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opc, "l\tp$cop, cr$CRd, [$base], $option"> {
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let Inst{31-28} = op31_28;
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let Inst{24} = 0; // P = 0
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let Inst{23} = 1; // U = 1
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let Inst{21} = 0; // W = 0
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let Inst{22} = 1; // D = 1
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let Inst{20} = load;
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}
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}
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defm LDC : LdStCop<{?,?,?,?}, 1, "ldc">;
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defm LDC2 : LdStCop<0b1111, 1, "ldc2">;
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defm STC : LdStCop<{?,?,?,?}, 0, "stc">;
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defm STC2 : LdStCop<0b1111, 0, "stc2">;
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def MCR : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
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def MCR : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
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GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
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GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
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NoItinerary, "mcr", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
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NoItinerary, "mcr", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
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@ -2284,14 +2395,28 @@ def MRSsys : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary,"mrs","\t$dst, spsr",
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}
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}
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// FIXME: mask is ignored for the time being.
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// FIXME: mask is ignored for the time being.
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def MSR : ABI<0b0001,(outs),(ins GPR:$src), NoItinerary, "mrs", "\tcpsr, $src",
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def MSR : ABI<0b0001,(outs),(ins GPR:$src), NoItinerary, "msr", "\tcpsr, $src",
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[/* For disassembly only; pattern left blank */]> {
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[/* For disassembly only; pattern left blank */]> {
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let Inst{23-20} = 0b0010;
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let Inst{23-20} = 0b0010;
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let Inst{7-4} = 0b0000;
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let Inst{7-4} = 0b0000;
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}
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}
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// FIXME: mask is ignored for the time being.
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// FIXME: mask is ignored for the time being.
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def MSRsys : ABI<0b0001,(outs),(ins GPR:$src),NoItinerary,"mrs","\tspsr, $src",
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def MSRi : ABI<0b0011,(outs),(ins so_imm:$a), NoItinerary, "msr", "\tcpsr, $a",
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[/* For disassembly only; pattern left blank */]> {
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let Inst{23-20} = 0b0010;
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let Inst{7-4} = 0b0000;
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}
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// FIXME: mask is ignored for the time being.
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def MSRsys : ABI<0b0001,(outs),(ins GPR:$src),NoItinerary,"msr","\tspsr, $src",
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[/* For disassembly only; pattern left blank */]> {
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let Inst{23-20} = 0b0110;
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let Inst{7-4} = 0b0000;
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}
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// FIXME: mask is ignored for the time being.
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def MSRsysi : ABI<0b0011,(outs),(ins so_imm:$a),NoItinerary,"msr","\tspsr, $a",
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[/* For disassembly only; pattern left blank */]> {
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[/* For disassembly only; pattern left blank */]> {
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let Inst{23-20} = 0b0110;
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let Inst{23-20} = 0b0110;
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let Inst{7-4} = 0b0000;
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let Inst{7-4} = 0b0000;
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