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Allow targets to specify the MachO CPUType/CPUSubtype information. 

llvm-svn: 118288
This commit is contained in:
Jim Grosbach 2010-11-05 18:48:58 +00:00
parent c75bb744e1
commit 46c2acbcb4
4 changed files with 24 additions and 11 deletions
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3
llvm/include/llvm/MC/MachObjectWriter.h
View File

@ -25,7 +25,8 @@ class MachObjectWriter : public MCObjectWriter {
void *Impl;
public:
MachObjectWriter(raw_ostream &OS, bool Is64Bit, bool IsLittleEndian = true);
MachObjectWriter(raw_ostream &OS, bool Is64Bit, uint32_t CPUType,
uint32_t CPUSubtype, bool IsLittleEndian = true);
virtual ~MachObjectWriter();
virtual void ExecutePostLayoutBinding(MCAssembler &Asm);

20
llvm/lib/MC/MachObjectWriter.cpp
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@ -290,9 +290,14 @@ class MachObjectWriterImpl {
unsigned Is64Bit : 1;
uint32_t CPUType;
uint32_t CPUSubtype;
public:
MachObjectWriterImpl(MachObjectWriter *_Writer, bool _Is64Bit)
: Writer(_Writer), OS(Writer->getStream()), Is64Bit(_Is64Bit) {
MachObjectWriterImpl(MachObjectWriter *_Writer, bool _Is64Bit,
uint32_t _CPUType, uint32_t _CPUSubtype)
: Writer(_Writer), OS(Writer->getStream()), Is64Bit(_Is64Bit),
CPUType(_CPUType), CPUSubtype(_CPUSubtype) {
}
void Write8(uint8_t Value) { Writer->Write8(Value); }
@ -319,10 +324,9 @@ public:
Write32(Is64Bit ? Header_Magic64 : Header_Magic32);
// FIXME: Support cputype.
Write32(Is64Bit ? MachO::CPUTypeX86_64 : MachO::CPUTypeI386);
// FIXME: Support cpusubtype.
Write32(MachO::CPUSubType_I386_ALL);
Write32(CPUType);
Write32(CPUSubtype);
Write32(HFT_Object);
Write32(NumLoadCommands); // Object files have a single load command, the
// segment.
@ -1329,10 +1333,12 @@ public:
MachObjectWriter::MachObjectWriter(raw_ostream &OS,
bool Is64Bit,
uint32_t CPUType,
uint32_t CPUSubtype,
bool IsLittleEndian)
: MCObjectWriter(OS, IsLittleEndian)
{
Impl = new MachObjectWriterImpl(this, Is64Bit);
Impl = new MachObjectWriterImpl(this, Is64Bit, CPUType, CPUSubtype);
}
MachObjectWriter::~MachObjectWriter() {

5
llvm/lib/Target/ARM/ARMAsmBackend.cpp
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@ -20,6 +20,7 @@
#include "llvm/MC/MCSectionMachO.h"
#include "llvm/MC/MachObjectWriter.h"
#include "llvm/Support/ELF.h"
#include "llvm/Support/MachO.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetRegistry.h"
@ -128,7 +129,9 @@ public:
}
MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
return new MachObjectWriter(OS, /*Is64Bit=*/false);
// FIXME: Subtarget info should be derived. Force v7 for now.
return new MachObjectWriter(OS, /*Is64Bit=*/false, MachO::CPUTypeARM,
MachO::CPUSubType_ARM_V7);
}
virtual bool doesSectionRequireSymbols(const MCSection &Section) const {

7
llvm/lib/Target/X86/X86AsmBackend.cpp
View File

@ -21,6 +21,7 @@
#include "llvm/MC/MCSectionMachO.h"
#include "llvm/MC/MachObjectWriter.h"
#include "llvm/Support/ELF.h"
#include "llvm/Support/MachO.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetRegistry.h"
@ -396,7 +397,8 @@ public:
}
MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
return new MachObjectWriter(OS, /*Is64Bit=*/false);
return new MachObjectWriter(OS, /*Is64Bit=*/false, MachO::CPUTypeI386,
MachO::CPUSubType_I386_ALL);
}
};
@ -412,7 +414,8 @@ public:
}
MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
return new MachObjectWriter(OS, /*Is64Bit=*/true);
return new MachObjectWriter(OS, /*Is64Bit=*/true, MachO::CPUTypeX86_64,
MachO::CPUSubType_I386_ALL);
}
virtual bool doesSectionRequireSymbols(const MCSection &Section) const {