diff --git a/llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp b/llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
index 0f4d84ea2b05..c90493454ade 100644
--- a/llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
@@ -556,9 +556,9 @@ void IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
 	// then load 1 into the same reg iff the predicate to store is 1
         SDOperand Tmp;
         Select(Tmp, N->getOperand(1));
-        CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial,
-                              CurDAG->getConstant(1, MVT::i64),
-                              Tmp);
+        Tmp = SDOperand(CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial,
+                                              CurDAG->getConstant(1, MVT::i64),
+                                              Tmp), 0);
         Result = CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain);
         return;
       }