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AMDGPU/GlobalISel: Fix broken tests 

llvm-svn: 366688
This commit is contained in:
Matt Arsenault 2019-07-22 13:33:11 +00:00
parent 5418be85e8
commit 4668ea4072
9 changed files with 54 additions and 54 deletions
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12
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-and.mir
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@ -14,10 +14,10 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; CHECK: [[COPY2:%[0-9]+]]:vgpr(p1) = COPY [[COPY]](p1)
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK: [[ATOMICRMW_ADD:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_ADD [[COPY2]](p1), [[COPY3]] :: (load store seq_cst 4, addrspace 1)
; CHECK: [[ATOMICRMW_AND:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_AND [[COPY2]](p1), [[COPY3]] :: (load store seq_cst 4, addrspace 1)
%0:_(p1) = COPY $sgpr0_sgpr1
%1:_(s32) = COPY $sgpr2
%2:_(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 4, addrspace 1)
%2:_(s32) = G_ATOMICRMW_AND %0, %1 :: (load store seq_cst 4, addrspace 1)
...
---
@ -32,10 +32,10 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; CHECK: [[COPY2:%[0-9]+]]:vgpr(p0) = COPY [[COPY]](p0)
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK: [[ATOMICRMW_ADD:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_ADD [[COPY2]](p0), [[COPY3]] :: (load store seq_cst 4)
; CHECK: [[ATOMICRMW_AND:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_AND [[COPY2]](p0), [[COPY3]] :: (load store seq_cst 4)
%0:_(p0) = COPY $sgpr0_sgpr1
%1:_(s32) = COPY $sgpr2
%2:_(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 4, addrspace 0)
%2:_(s32) = G_ATOMICRMW_AND %0, %1 :: (load store seq_cst 4, addrspace 0)
...
---
@ -50,8 +50,8 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[COPY2:%[0-9]+]]:vgpr(p3) = COPY [[COPY]](p3)
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK: [[ATOMICRMW_ADD:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_ADD [[COPY2]](p3), [[COPY3]] :: (load store seq_cst 4, addrspace 3)
; CHECK: [[ATOMICRMW_AND:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_AND [[COPY2]](p3), [[COPY3]] :: (load store seq_cst 4, addrspace 3)
%0:_(p3) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 4, addrspace 3)
%2:_(s32) = G_ATOMICRMW_AND %0, %1 :: (load store seq_cst 4, addrspace 3)
...

12
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-max.mir
View File

@ -14,10 +14,10 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; CHECK: [[COPY2:%[0-9]+]]:vgpr(p1) = COPY [[COPY]](p1)
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK: [[ATOMICRMW_ADD:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_ADD [[COPY2]](p1), [[COPY3]] :: (load store seq_cst 4, addrspace 1)
; CHECK: [[ATOMICRMW_MAX:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_MAX [[COPY2]](p1), [[COPY3]] :: (load store seq_cst 4, addrspace 1)
%0:_(p1) = COPY $sgpr0_sgpr1
%1:_(s32) = COPY $sgpr2
%2:_(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 4, addrspace 1)
%2:_(s32) = G_ATOMICRMW_MAX %0, %1 :: (load store seq_cst 4, addrspace 1)
...
---
@ -32,10 +32,10 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; CHECK: [[COPY2:%[0-9]+]]:vgpr(p0) = COPY [[COPY]](p0)
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK: [[ATOMICRMW_ADD:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_ADD [[COPY2]](p0), [[COPY3]] :: (load store seq_cst 4)
; CHECK: [[ATOMICRMW_MAX:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_MAX [[COPY2]](p0), [[COPY3]] :: (load store seq_cst 4)
%0:_(p0) = COPY $sgpr0_sgpr1
%1:_(s32) = COPY $sgpr2
%2:_(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 4, addrspace 0)
%2:_(s32) = G_ATOMICRMW_MAX %0, %1 :: (load store seq_cst 4, addrspace 0)
...
---
@ -50,8 +50,8 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[COPY2:%[0-9]+]]:vgpr(p3) = COPY [[COPY]](p3)
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK: [[ATOMICRMW_ADD:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_ADD [[COPY2]](p3), [[COPY3]] :: (load store seq_cst 4, addrspace 3)
; CHECK: [[ATOMICRMW_MAX:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_MAX [[COPY2]](p3), [[COPY3]] :: (load store seq_cst 4, addrspace 3)
%0:_(p3) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 4, addrspace 3)
%2:_(s32) = G_ATOMICRMW_MAX %0, %1 :: (load store seq_cst 4, addrspace 3)
...

12
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-min.mir
View File

@ -14,10 +14,10 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; CHECK: [[COPY2:%[0-9]+]]:vgpr(p1) = COPY [[COPY]](p1)
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK: [[ATOMICRMW_ADD:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_ADD [[COPY2]](p1), [[COPY3]] :: (load store seq_cst 4, addrspace 1)
; CHECK: [[ATOMICRMW_MIN:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_MIN [[COPY2]](p1), [[COPY3]] :: (load store seq_cst 4, addrspace 1)
%0:_(p1) = COPY $sgpr0_sgpr1
%1:_(s32) = COPY $sgpr2
%2:_(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 4, addrspace 1)
%2:_(s32) = G_ATOMICRMW_MIN %0, %1 :: (load store seq_cst 4, addrspace 1)
...
---
@ -32,10 +32,10 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; CHECK: [[COPY2:%[0-9]+]]:vgpr(p0) = COPY [[COPY]](p0)
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK: [[ATOMICRMW_ADD:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_ADD [[COPY2]](p0), [[COPY3]] :: (load store seq_cst 4)
; CHECK: [[ATOMICRMW_MIN:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_MIN [[COPY2]](p0), [[COPY3]] :: (load store seq_cst 4)
%0:_(p0) = COPY $sgpr0_sgpr1
%1:_(s32) = COPY $sgpr2
%2:_(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 4, addrspace 0)
%2:_(s32) = G_ATOMICRMW_MIN %0, %1 :: (load store seq_cst 4, addrspace 0)
...
---
@ -50,8 +50,8 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[COPY2:%[0-9]+]]:vgpr(p3) = COPY [[COPY]](p3)
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK: [[ATOMICRMW_ADD:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_ADD [[COPY2]](p3), [[COPY3]] :: (load store seq_cst 4, addrspace 3)
; CHECK: [[ATOMICRMW_MIN:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_MIN [[COPY2]](p3), [[COPY3]] :: (load store seq_cst 4, addrspace 3)
%0:_(p3) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 4, addrspace 3)
%2:_(s32) = G_ATOMICRMW_MIN %0, %1 :: (load store seq_cst 4, addrspace 3)
...

12
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-or.mir
View File

@ -14,10 +14,10 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; CHECK: [[COPY2:%[0-9]+]]:vgpr(p1) = COPY [[COPY]](p1)
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK: [[ATOMICRMW_ADD:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_ADD [[COPY2]](p1), [[COPY3]] :: (load store seq_cst 4, addrspace 1)
; CHECK: [[ATOMICRMW_OR:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_OR [[COPY2]](p1), [[COPY3]] :: (load store seq_cst 4, addrspace 1)
%0:_(p1) = COPY $sgpr0_sgpr1
%1:_(s32) = COPY $sgpr2
%2:_(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 4, addrspace 1)
%2:_(s32) = G_ATOMICRMW_OR %0, %1 :: (load store seq_cst 4, addrspace 1)
...
---
@ -32,10 +32,10 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; CHECK: [[COPY2:%[0-9]+]]:vgpr(p0) = COPY [[COPY]](p0)
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK: [[ATOMICRMW_ADD:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_ADD [[COPY2]](p0), [[COPY3]] :: (load store seq_cst 4)
; CHECK: [[ATOMICRMW_OR:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_OR [[COPY2]](p0), [[COPY3]] :: (load store seq_cst 4)
%0:_(p0) = COPY $sgpr0_sgpr1
%1:_(s32) = COPY $sgpr2
%2:_(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 4, addrspace 0)
%2:_(s32) = G_ATOMICRMW_OR %0, %1 :: (load store seq_cst 4, addrspace 0)
...
---
@ -50,8 +50,8 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[COPY2:%[0-9]+]]:vgpr(p3) = COPY [[COPY]](p3)
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK: [[ATOMICRMW_ADD:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_ADD [[COPY2]](p3), [[COPY3]] :: (load store seq_cst 4, addrspace 3)
; CHECK: [[ATOMICRMW_OR:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_OR [[COPY2]](p3), [[COPY3]] :: (load store seq_cst 4, addrspace 3)
%0:_(p3) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 4, addrspace 3)
%2:_(s32) = G_ATOMICRMW_OR %0, %1 :: (load store seq_cst 4, addrspace 3)
...

12
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-sub.mir
View File

@ -14,10 +14,10 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; CHECK: [[COPY2:%[0-9]+]]:vgpr(p1) = COPY [[COPY]](p1)
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK: [[ATOMICRMW_ADD:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_ADD [[COPY2]](p1), [[COPY3]] :: (load store seq_cst 4, addrspace 1)
; CHECK: [[ATOMICRMW_SUB:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_SUB [[COPY2]](p1), [[COPY3]] :: (load store seq_cst 4, addrspace 1)
%0:_(p1) = COPY $sgpr0_sgpr1
%1:_(s32) = COPY $sgpr2
%2:_(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 4, addrspace 1)
%2:_(s32) = G_ATOMICRMW_SUB %0, %1 :: (load store seq_cst 4, addrspace 1)
...
---
@ -32,10 +32,10 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; CHECK: [[COPY2:%[0-9]+]]:vgpr(p0) = COPY [[COPY]](p0)
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK: [[ATOMICRMW_ADD:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_ADD [[COPY2]](p0), [[COPY3]] :: (load store seq_cst 4)
; CHECK: [[ATOMICRMW_SUB:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_SUB [[COPY2]](p0), [[COPY3]] :: (load store seq_cst 4)
%0:_(p0) = COPY $sgpr0_sgpr1
%1:_(s32) = COPY $sgpr2
%2:_(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 4, addrspace 0)
%2:_(s32) = G_ATOMICRMW_SUB %0, %1 :: (load store seq_cst 4, addrspace 0)
...
---
@ -50,8 +50,8 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[COPY2:%[0-9]+]]:vgpr(p3) = COPY [[COPY]](p3)
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK: [[ATOMICRMW_ADD:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_ADD [[COPY2]](p3), [[COPY3]] :: (load store seq_cst 4, addrspace 3)
; CHECK: [[ATOMICRMW_SUB:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_SUB [[COPY2]](p3), [[COPY3]] :: (load store seq_cst 4, addrspace 3)
%0:_(p3) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 4, addrspace 3)
%2:_(s32) = G_ATOMICRMW_SUB %0, %1 :: (load store seq_cst 4, addrspace 3)
...

12
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umax.mir
View File

@ -14,10 +14,10 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; CHECK: [[COPY2:%[0-9]+]]:vgpr(p1) = COPY [[COPY]](p1)
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK: [[ATOMICRMW_ADD:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_ADD [[COPY2]](p1), [[COPY3]] :: (load store seq_cst 4, addrspace 1)
; CHECK: [[ATOMICRMW_UMAX:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_UMAX [[COPY2]](p1), [[COPY3]] :: (load store seq_cst 4, addrspace 1)
%0:_(p1) = COPY $sgpr0_sgpr1
%1:_(s32) = COPY $sgpr2
%2:_(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 4, addrspace 1)
%2:_(s32) = G_ATOMICRMW_UMAX %0, %1 :: (load store seq_cst 4, addrspace 1)
...
---
@ -32,10 +32,10 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; CHECK: [[COPY2:%[0-9]+]]:vgpr(p0) = COPY [[COPY]](p0)
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK: [[ATOMICRMW_ADD:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_ADD [[COPY2]](p0), [[COPY3]] :: (load store seq_cst 4)
; CHECK: [[ATOMICRMW_UMAX:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_UMAX [[COPY2]](p0), [[COPY3]] :: (load store seq_cst 4)
%0:_(p0) = COPY $sgpr0_sgpr1
%1:_(s32) = COPY $sgpr2
%2:_(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 4, addrspace 0)
%2:_(s32) = G_ATOMICRMW_UMAX %0, %1 :: (load store seq_cst 4, addrspace 0)
...
---
@ -50,8 +50,8 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[COPY2:%[0-9]+]]:vgpr(p3) = COPY [[COPY]](p3)
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK: [[ATOMICRMW_ADD:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_ADD [[COPY2]](p3), [[COPY3]] :: (load store seq_cst 4, addrspace 3)
; CHECK: [[ATOMICRMW_UMAX:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_UMAX [[COPY2]](p3), [[COPY3]] :: (load store seq_cst 4, addrspace 3)
%0:_(p3) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 4, addrspace 3)
%2:_(s32) = G_ATOMICRMW_UMAX %0, %1 :: (load store seq_cst 4, addrspace 3)
...

12
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umin.mir
View File

@ -14,10 +14,10 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; CHECK: [[COPY2:%[0-9]+]]:vgpr(p1) = COPY [[COPY]](p1)
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK: [[ATOMICRMW_ADD:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_ADD [[COPY2]](p1), [[COPY3]] :: (load store seq_cst 4, addrspace 1)
; CHECK: [[ATOMICRMW_UMIN:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_UMIN [[COPY2]](p1), [[COPY3]] :: (load store seq_cst 4, addrspace 1)
%0:_(p1) = COPY $sgpr0_sgpr1
%1:_(s32) = COPY $sgpr2
%2:_(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 4, addrspace 1)
%2:_(s32) = G_ATOMICRMW_UMIN %0, %1 :: (load store seq_cst 4, addrspace 1)
...
---
@ -32,10 +32,10 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; CHECK: [[COPY2:%[0-9]+]]:vgpr(p0) = COPY [[COPY]](p0)
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK: [[ATOMICRMW_ADD:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_ADD [[COPY2]](p0), [[COPY3]] :: (load store seq_cst 4)
; CHECK: [[ATOMICRMW_UMIN:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_UMIN [[COPY2]](p0), [[COPY3]] :: (load store seq_cst 4)
%0:_(p0) = COPY $sgpr0_sgpr1
%1:_(s32) = COPY $sgpr2
%2:_(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 4, addrspace 0)
%2:_(s32) = G_ATOMICRMW_UMIN %0, %1 :: (load store seq_cst 4, addrspace 0)
...
---
@ -50,8 +50,8 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[COPY2:%[0-9]+]]:vgpr(p3) = COPY [[COPY]](p3)
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK: [[ATOMICRMW_ADD:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_ADD [[COPY2]](p3), [[COPY3]] :: (load store seq_cst 4, addrspace 3)
; CHECK: [[ATOMICRMW_UMIN:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_UMIN [[COPY2]](p3), [[COPY3]] :: (load store seq_cst 4, addrspace 3)
%0:_(p3) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 4, addrspace 3)
%2:_(s32) = G_ATOMICRMW_UMIN %0, %1 :: (load store seq_cst 4, addrspace 3)
...

12
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xchg.mir
View File

@ -14,10 +14,10 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; CHECK: [[COPY2:%[0-9]+]]:vgpr(p1) = COPY [[COPY]](p1)
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK: [[ATOMICRMW_ADD:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_ADD [[COPY2]](p1), [[COPY3]] :: (load store seq_cst 4, addrspace 1)
; CHECK: [[ATOMICRMW_XCHG:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_XCHG [[COPY2]](p1), [[COPY3]] :: (load store seq_cst 4, addrspace 1)
%0:_(p1) = COPY $sgpr0_sgpr1
%1:_(s32) = COPY $sgpr2
%2:_(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 4, addrspace 1)
%2:_(s32) = G_ATOMICRMW_XCHG %0, %1 :: (load store seq_cst 4, addrspace 1)
...
---
@ -32,10 +32,10 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; CHECK: [[COPY2:%[0-9]+]]:vgpr(p0) = COPY [[COPY]](p0)
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK: [[ATOMICRMW_ADD:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_ADD [[COPY2]](p0), [[COPY3]] :: (load store seq_cst 4)
; CHECK: [[ATOMICRMW_XCHG:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_XCHG [[COPY2]](p0), [[COPY3]] :: (load store seq_cst 4)
%0:_(p0) = COPY $sgpr0_sgpr1
%1:_(s32) = COPY $sgpr2
%2:_(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 4, addrspace 0)
%2:_(s32) = G_ATOMICRMW_XCHG %0, %1 :: (load store seq_cst 4, addrspace 0)
...
---
@ -50,8 +50,8 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[COPY2:%[0-9]+]]:vgpr(p3) = COPY [[COPY]](p3)
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK: [[ATOMICRMW_ADD:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_ADD [[COPY2]](p3), [[COPY3]] :: (load store seq_cst 4, addrspace 3)
; CHECK: [[ATOMICRMW_XCHG:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_XCHG [[COPY2]](p3), [[COPY3]] :: (load store seq_cst 4, addrspace 3)
%0:_(p3) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 4, addrspace 3)
%2:_(s32) = G_ATOMICRMW_XCHG %0, %1 :: (load store seq_cst 4, addrspace 3)
...

12
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xor.mir
View File

@ -14,10 +14,10 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; CHECK: [[COPY2:%[0-9]+]]:vgpr(p1) = COPY [[COPY]](p1)
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK: [[ATOMICRMW_ADD:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_ADD [[COPY2]](p1), [[COPY3]] :: (load store seq_cst 4, addrspace 1)
; CHECK: [[ATOMICRMW_XOR:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_XOR [[COPY2]](p1), [[COPY3]] :: (load store seq_cst 4, addrspace 1)
%0:_(p1) = COPY $sgpr0_sgpr1
%1:_(s32) = COPY $sgpr2
%2:_(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 4, addrspace 1)
%2:_(s32) = G_ATOMICRMW_XOR %0, %1 :: (load store seq_cst 4, addrspace 1)
...
---
@ -32,10 +32,10 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; CHECK: [[COPY2:%[0-9]+]]:vgpr(p0) = COPY [[COPY]](p0)
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK: [[ATOMICRMW_ADD:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_ADD [[COPY2]](p0), [[COPY3]] :: (load store seq_cst 4)
; CHECK: [[ATOMICRMW_XOR:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_XOR [[COPY2]](p0), [[COPY3]] :: (load store seq_cst 4)
%0:_(p0) = COPY $sgpr0_sgpr1
%1:_(s32) = COPY $sgpr2
%2:_(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 4, addrspace 0)
%2:_(s32) = G_ATOMICRMW_XOR %0, %1 :: (load store seq_cst 4, addrspace 0)
...
---
@ -50,8 +50,8 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[COPY2:%[0-9]+]]:vgpr(p3) = COPY [[COPY]](p3)
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK: [[ATOMICRMW_ADD:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_ADD [[COPY2]](p3), [[COPY3]] :: (load store seq_cst 4, addrspace 3)
; CHECK: [[ATOMICRMW_XOR:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_XOR [[COPY2]](p3), [[COPY3]] :: (load store seq_cst 4, addrspace 3)
%0:_(p3) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 4, addrspace 3)
%2:_(s32) = G_ATOMICRMW_XOR %0, %1 :: (load store seq_cst 4, addrspace 3)
...