[AMDGPU] Eliminate SGPR to VGPR copy when possible
SGPRs are generally cheaper, so try to use them over VGPRs. Differential Revision: https://reviews.llvm.org/D34130 llvm-svn: 305815
This commit is contained in:
Stanislav Mekhanoshin
parent
7f67b35901
commit
465a1ff193
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@ -174,6 +174,31 @@ static bool isSGPRToVGPRCopy(const TargetRegisterClass *SrcRC,
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return TRI.isSGPRClass(SrcRC) && TRI.hasVGPRs(DstRC);
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}
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static bool tryChangeVGPRtoSGPRinCopy(MachineInstr &MI,
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const SIRegisterInfo *TRI,
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const SIInstrInfo *TII) {
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MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
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auto &Src = MI.getOperand(1);
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unsigned DstReg = MI.getOperand(0).getReg();
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unsigned SrcReg = Src.getReg();
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if (!TargetRegisterInfo::isVirtualRegister(SrcReg) ||
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!TargetRegisterInfo::isVirtualRegister(DstReg))
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return false;
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for (const auto &MO : MRI.reg_nodbg_operands(DstReg)) {
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const auto *UseMI = MO.getParent();
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if (UseMI == &MI)
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continue;
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if (MO.isDef() || UseMI->getParent() != MI.getParent() ||
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UseMI->getOpcode() <= TargetOpcode::GENERIC_OP_END ||
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!TII->isOperandLegal(*UseMI, UseMI->getOperandNo(&MO), &Src))
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return false;
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}
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// Change VGPR to SGPR destination.
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MRI.setRegClass(DstReg, TRI->getEquivalentSGPRClass(MRI.getRegClass(DstReg)));
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return true;
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}
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// Distribute an SGPR->VGPR copy of a REG_SEQUENCE into a VGPR REG_SEQUENCE.
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//
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// SGPRx = ...
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@ -214,6 +239,9 @@ static bool foldVGPRCopyIntoRegSequence(MachineInstr &MI,
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if (!isSGPRToVGPRCopy(SrcRC, DstRC, *TRI))
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return false;
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if (tryChangeVGPRtoSGPRinCopy(CopyUse, TRI, TII))
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return true;
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// TODO: Could have multiple extracts?
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unsigned SubReg = CopyUse.getOperand(1).getSubReg();
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if (SubReg != AMDGPU::NoSubRegister)
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@ -563,6 +591,8 @@ bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) {
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break;
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}
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TII->moveToVALU(MI);
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} else if (isSGPRToVGPRCopy(SrcRC, DstRC, *TRI)) {
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tryChangeVGPRtoSGPRinCopy(MI, TRI, TII);
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}
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break;
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@ -4,7 +4,7 @@
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declare i64 @llvm.amdgcn.mqsad.pk.u16.u8(i64, i32, i64) #0
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; GCN-LABEL: {{^}}v_mqsad_pk_u16_u8:
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; GCN: v_mqsad_pk_u16_u8 v[0:1], v[4:5], s{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}]
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; GCN: v_mqsad_pk_u16_u8 v[0:1], v[4:5], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}]
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; GCN-DAG: v_mov_b32_e32 v5, v1
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; GCN-DAG: v_mov_b32_e32 v4, v0
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define amdgpu_kernel void @v_mqsad_pk_u16_u8(i64 addrspace(1)* %out, i64 %src) {
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@ -4,7 +4,7 @@
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declare i64 @llvm.amdgcn.qsad.pk.u16.u8(i64, i32, i64) #0
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; GCN-LABEL: {{^}}v_qsad_pk_u16_u8:
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; GCN: v_qsad_pk_u16_u8 v[0:1], v[4:5], s{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}]
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; GCN: v_qsad_pk_u16_u8 v[0:1], v[4:5], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}]
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; GCN-DAG: v_mov_b32_e32 v5, v1
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; GCN-DAG: v_mov_b32_e32 v4, v0
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define amdgpu_kernel void @v_qsad_pk_u16_u8(i64 addrspace(1)* %out, i64 %src) {
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@ -0,0 +1,341 @@
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# RUN: llc -march=amdgcn -run-pass si-fix-sgpr-copies,si-fold-operands,dead-mi-elimination -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
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# Check that constant is in SGPR registers
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# GCN-LABEL: {{^}}name: const_to_sgpr{{$}}
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# GCN: %[[HI:[0-9]+]] = S_MOV_B32 0
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# GCN-NEXT: %[[LO:[0-9]+]] = S_MOV_B32 1048576
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# GCN-NEXT: %[[SGPR_PAIR:[0-9]+]] = REG_SEQUENCE killed %[[LO]], 1, killed %[[HI]], 2
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# GCN-NEXT: V_CMP_LT_U64_e64 killed %{{[0-9]+}}, %[[SGPR_PAIR]], implicit %exec
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# GCN-LABEL: {{^}}name: const_to_sgpr_multiple_use{{$}}
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# GCN: %[[HI:[0-9]+]] = S_MOV_B32 0
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# GCN-NEXT: %[[LO:[0-9]+]] = S_MOV_B32 1048576
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# GCN-NEXT: %[[SGPR_PAIR:[0-9]+]] = REG_SEQUENCE killed %[[LO]], 1, killed %[[HI]], 2
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# GCN-NEXT: V_CMP_LT_U64_e64 killed %{{[0-9]+}}, %[[SGPR_PAIR]], implicit %exec
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# GCN-NEXT: V_CMP_LT_U64_e64 killed %{{[0-9]+}}, %[[SGPR_PAIR]], implicit %exec
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# GCN-LABEL: {{^}}name: const_to_sgpr_subreg{{$}}
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# GCN: %[[OP0:[0-9]+]] = REG_SEQUENCE killed %{{[0-9]+}}, 1, killed %{{[0-9]+}}, 2
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# GCN-NEXT: V_CMP_LT_U32_e64 killed %[[OP0]].sub0, 12, implicit %exec
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--- |
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define amdgpu_kernel void @const_to_sgpr(i32 addrspace(1)* nocapture %arg, i64 %id) {
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bb:
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br i1 undef, label %bb1, label %bb2
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bb1: ; preds = %bb
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br label %bb2
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bb2: ; preds = %bb1, %bb
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ret void
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}
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define amdgpu_kernel void @const_to_sgpr_multiple_use(i32 addrspace(1)* nocapture %arg, i64 %id1, i64 %id2) {
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bb:
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br i1 undef, label %bb1, label %bb2
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bb1: ; preds = %bb
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br label %bb2
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bb2: ; preds = %bb1, %bb
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ret void
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}
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define amdgpu_kernel void @const_to_sgpr_subreg(i32 addrspace(1)* nocapture %arg, i64 %id) {
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bb:
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br i1 undef, label %bb1, label %bb2
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bb1: ; preds = %bb
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br label %bb2
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bb2: ; preds = %bb1, %bb
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ret void
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}
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...
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---
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name: const_to_sgpr
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alignment: 0
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: sreg_64 }
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- { id: 1, class: sreg_64 }
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- { id: 2, class: vgpr_32 }
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- { id: 3, class: sgpr_64 }
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- { id: 4, class: sreg_32_xm0 }
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- { id: 5, class: sgpr_32 }
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- { id: 6, class: sreg_64 }
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- { id: 7, class: sreg_64_xexec }
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- { id: 8, class: sreg_64_xexec }
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- { id: 9, class: sreg_32 }
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- { id: 10, class: sreg_64 }
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- { id: 11, class: sreg_32_xm0 }
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- { id: 12, class: sreg_32_xm0 }
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- { id: 13, class: sreg_32_xm0 }
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- { id: 14, class: sreg_32_xm0 }
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- { id: 15, class: sreg_32_xm0 }
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- { id: 16, class: sreg_32_xm0 }
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- { id: 17, class: sreg_64 }
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- { id: 18, class: sreg_32_xm0 }
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- { id: 19, class: sreg_32_xm0 }
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- { id: 20, class: sreg_64 }
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- { id: 21, class: sreg_64 }
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- { id: 22, class: vreg_64 }
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- { id: 23, class: sreg_32_xm0 }
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- { id: 24, class: sreg_64 }
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- { id: 25, class: sreg_32_xm0 }
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- { id: 26, class: sreg_32_xm0 }
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- { id: 27, class: sgpr_64 }
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- { id: 28, class: sgpr_128 }
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- { id: 29, class: vgpr_32 }
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- { id: 30, class: vreg_64 }
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liveins:
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- { reg: '%vgpr0', virtual-reg: '%2' }
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- { reg: '%sgpr0_sgpr1', virtual-reg: '%3' }
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body: |
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bb.0.bb:
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successors: %bb.1.bb1(0x40000000), %bb.2.bb2(0x40000000)
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liveins: %vgpr0, %sgpr0_sgpr1
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%3 = COPY %sgpr0_sgpr1
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%2 = COPY %vgpr0
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%7 = S_LOAD_DWORDX2_IMM %3, 9, 0
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%8 = S_LOAD_DWORDX2_IMM %3, 11, 0
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%6 = COPY %7
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%9 = S_MOV_B32 0
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%10 = REG_SEQUENCE %2, 1, killed %9, 2
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%0 = COPY %10
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%11 = COPY %10.sub0
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%12 = COPY %10.sub1
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%13 = COPY %8.sub0
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%14 = COPY %8.sub1
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%15 = S_ADD_U32 killed %11, killed %13, implicit-def %scc
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%16 = S_ADDC_U32 killed %12, killed %14, implicit-def dead %scc, implicit %scc
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%17 = REG_SEQUENCE killed %15, 1, killed %16, 2
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%18 = S_MOV_B32 0
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%19 = S_MOV_B32 1048576
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%20 = REG_SEQUENCE killed %19, 1, killed %18, 2
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%22 = COPY killed %20
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%21 = V_CMP_LT_U64_e64 killed %17, %22, implicit %exec
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%1 = SI_IF killed %21, %bb.2.bb2, implicit-def dead %exec, implicit-def dead %scc, implicit %exec
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S_BRANCH %bb.1.bb1
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bb.1.bb1:
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successors: %bb.2.bb2(0x80000000)
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%23 = S_MOV_B32 2
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%24 = S_LSHL_B64 %0, killed %23, implicit-def dead %scc
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%25 = S_MOV_B32 61440
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%26 = S_MOV_B32 0
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%27 = REG_SEQUENCE killed %26, 1, killed %25, 2
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%28 = REG_SEQUENCE %6, 17, killed %27, 18
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%29 = V_MOV_B32_e32 0, implicit %exec
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%30 = COPY %24
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BUFFER_STORE_DWORD_ADDR64 killed %29, killed %30, killed %28, 0, 0, 0, 0, 0, implicit %exec
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bb.2.bb2:
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SI_END_CF %1, implicit-def dead %exec, implicit-def dead %scc, implicit %exec
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S_ENDPGM
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...
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---
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name: const_to_sgpr_multiple_use
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alignment: 0
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: sreg_64 }
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- { id: 1, class: sreg_64 }
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- { id: 2, class: vgpr_32 }
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- { id: 3, class: sgpr_64 }
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- { id: 4, class: sreg_32_xm0 }
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- { id: 5, class: sgpr_32 }
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- { id: 6, class: sreg_64 }
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- { id: 7, class: sreg_64_xexec }
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- { id: 8, class: sreg_64_xexec }
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- { id: 9, class: sreg_64_xexec }
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- { id: 10, class: sreg_32 }
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- { id: 11, class: sreg_64 }
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- { id: 12, class: sreg_32_xm0 }
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- { id: 13, class: sreg_32_xm0 }
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- { id: 14, class: sreg_32_xm0 }
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- { id: 15, class: sreg_32_xm0 }
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- { id: 16, class: sreg_32_xm0 }
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- { id: 17, class: sreg_32_xm0 }
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- { id: 18, class: sreg_64 }
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- { id: 19, class: sreg_32_xm0 }
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- { id: 20, class: sreg_32_xm0 }
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- { id: 21, class: sreg_32_xm0 }
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- { id: 22, class: sreg_32_xm0 }
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- { id: 23, class: sreg_64 }
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- { id: 24, class: sreg_32_xm0 }
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- { id: 25, class: sreg_32_xm0 }
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- { id: 26, class: sreg_64 }
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- { id: 27, class: sreg_64 }
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- { id: 28, class: vreg_64 }
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- { id: 29, class: sreg_64 }
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- { id: 30, class: vreg_64 }
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- { id: 31, class: sreg_64 }
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- { id: 32, class: sreg_32_xm0 }
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- { id: 33, class: sreg_64 }
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- { id: 34, class: sreg_32_xm0 }
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- { id: 35, class: sreg_32_xm0 }
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- { id: 36, class: sgpr_64 }
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- { id: 37, class: sgpr_128 }
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- { id: 38, class: vgpr_32 }
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- { id: 39, class: vreg_64 }
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liveins:
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- { reg: '%vgpr0', virtual-reg: '%2' }
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- { reg: '%sgpr0_sgpr1', virtual-reg: '%3' }
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body: |
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bb.0.bb:
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successors: %bb.1.bb1(0x40000000), %bb.2.bb2(0x40000000)
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liveins: %vgpr0, %sgpr0_sgpr1
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%3 = COPY %sgpr0_sgpr1
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%2 = COPY %vgpr0
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%7 = S_LOAD_DWORDX2_IMM %3, 9, 0
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%8 = S_LOAD_DWORDX2_IMM %3, 11, 0
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%9 = S_LOAD_DWORDX2_IMM %3, 13, 0
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%6 = COPY %7
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%10 = S_MOV_B32 0
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%11 = REG_SEQUENCE %2, 1, killed %10, 2
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%0 = COPY %11
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%12 = COPY %11.sub0
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%13 = COPY %11.sub1
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%14 = COPY %8.sub0
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%15 = COPY %8.sub1
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%16 = S_ADD_U32 %12, killed %14, implicit-def %scc
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%17 = S_ADDC_U32 %13, killed %15, implicit-def dead %scc, implicit %scc
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%18 = REG_SEQUENCE killed %16, 1, killed %17, 2
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%19 = COPY %9.sub0
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%20 = COPY %9.sub1
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%21 = S_ADD_U32 %12, killed %19, implicit-def %scc
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%22 = S_ADDC_U32 %13, killed %20, implicit-def dead %scc, implicit %scc
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%23 = REG_SEQUENCE killed %21, 1, killed %22, 2
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%24 = S_MOV_B32 0
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%25 = S_MOV_B32 1048576
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%26 = REG_SEQUENCE killed %25, 1, killed %24, 2
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%28 = COPY %26
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%27 = V_CMP_LT_U64_e64 killed %18, %28, implicit %exec
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%29 = V_CMP_LT_U64_e64 killed %23, %28, implicit %exec
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%31 = S_AND_B64 killed %27, killed %29, implicit-def dead %scc
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%1 = SI_IF killed %31, %bb.2.bb2, implicit-def dead %exec, implicit-def dead %scc, implicit %exec
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S_BRANCH %bb.1.bb1
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bb.1.bb1:
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successors: %bb.2.bb2(0x80000000)
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%32 = S_MOV_B32 2
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%33 = S_LSHL_B64 %0, killed %32, implicit-def dead %scc
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%34 = S_MOV_B32 61440
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%35 = S_MOV_B32 0
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%36 = REG_SEQUENCE killed %35, 1, killed %34, 2
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%37 = REG_SEQUENCE %6, 17, killed %36, 18
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%38 = V_MOV_B32_e32 0, implicit %exec
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%39 = COPY %33
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BUFFER_STORE_DWORD_ADDR64 killed %38, killed %39, killed %37, 0, 0, 0, 0, 0, implicit %exec
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bb.2.bb2:
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SI_END_CF %1, implicit-def dead %exec, implicit-def dead %scc, implicit %exec
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S_ENDPGM
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...
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---
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name: const_to_sgpr_subreg
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alignment: 0
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: sreg_64 }
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- { id: 1, class: sreg_64 }
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- { id: 2, class: vgpr_32 }
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- { id: 3, class: sgpr_64 }
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- { id: 4, class: sreg_32_xm0 }
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- { id: 5, class: sgpr_32 }
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- { id: 6, class: sreg_64 }
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- { id: 7, class: sreg_64_xexec }
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- { id: 8, class: sreg_64_xexec }
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- { id: 9, class: sreg_32 }
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- { id: 10, class: sreg_64 }
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- { id: 11, class: sreg_32_xm0 }
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- { id: 12, class: sreg_32_xm0 }
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- { id: 13, class: sreg_32_xm0 }
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- { id: 14, class: sreg_32_xm0 }
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- { id: 15, class: sreg_32_xm0 }
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- { id: 16, class: sreg_32_xm0 }
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- { id: 17, class: sreg_64 }
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- { id: 18, class: sreg_32_xm0 }
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- { id: 19, class: sreg_32_xm0 }
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- { id: 20, class: sreg_64 }
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- { id: 21, class: sreg_64 }
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- { id: 22, class: vgpr_32 }
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- { id: 23, class: sreg_32_xm0 }
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- { id: 24, class: sreg_64 }
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- { id: 25, class: sreg_32_xm0 }
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- { id: 26, class: sreg_32_xm0 }
|
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- { id: 27, class: sgpr_64 }
|
||||
- { id: 28, class: sgpr_128 }
|
||||
- { id: 29, class: vgpr_32 }
|
||||
- { id: 30, class: vreg_64 }
|
||||
liveins:
|
||||
- { reg: '%vgpr0', virtual-reg: '%2' }
|
||||
- { reg: '%sgpr0_sgpr1', virtual-reg: '%3' }
|
||||
body: |
|
||||
bb.0.bb:
|
||||
successors: %bb.1.bb1(0x40000000), %bb.2.bb2(0x40000000)
|
||||
liveins: %vgpr0, %sgpr0_sgpr1
|
||||
|
||||
%3 = COPY %sgpr0_sgpr1
|
||||
%2 = COPY %vgpr0
|
||||
%7 = S_LOAD_DWORDX2_IMM %3, 9, 0
|
||||
%8 = S_LOAD_DWORDX2_IMM %3, 11, 0
|
||||
%6 = COPY %7
|
||||
%9 = S_MOV_B32 0
|
||||
%10 = REG_SEQUENCE %2, 1, killed %9, 2
|
||||
%0 = COPY %10
|
||||
%11 = COPY %10.sub0
|
||||
%12 = COPY %10.sub1
|
||||
%13 = COPY %8.sub0
|
||||
%14 = COPY %8.sub1
|
||||
%15 = S_ADD_U32 killed %11, killed %13, implicit-def %scc
|
||||
%16 = S_ADDC_U32 killed %12, killed %14, implicit-def dead %scc, implicit %scc
|
||||
%17 = REG_SEQUENCE killed %15, 1, killed %16, 2
|
||||
%18 = S_MOV_B32 12
|
||||
%19 = S_MOV_B32 1048576
|
||||
%20 = REG_SEQUENCE killed %19, 1, killed %18, 2
|
||||
%22 = COPY killed %20.sub1
|
||||
%21 = V_CMP_LT_U32_e64 killed %17.sub0, %22, implicit %exec
|
||||
%1 = SI_IF killed %21, %bb.2.bb2, implicit-def dead %exec, implicit-def dead %scc, implicit %exec
|
||||
S_BRANCH %bb.1.bb1
|
||||
|
||||
bb.1.bb1:
|
||||
successors: %bb.2.bb2(0x80000000)
|
||||
|
||||
%23 = S_MOV_B32 2
|
||||
%24 = S_LSHL_B64 %0, killed %23, implicit-def dead %scc
|
||||
%25 = S_MOV_B32 61440
|
||||
%26 = S_MOV_B32 0
|
||||
%27 = REG_SEQUENCE killed %26, 1, killed %25, 2
|
||||
%28 = REG_SEQUENCE %6, 17, killed %27, 18
|
||||
%29 = V_MOV_B32_e32 0, implicit %exec
|
||||
%30 = COPY %24
|
||||
BUFFER_STORE_DWORD_ADDR64 killed %29, killed %30, killed %28, 0, 0, 0, 0, 0, implicit %exec
|
||||
|
||||
bb.2.bb2:
|
||||
SI_END_CF %1, implicit-def dead %exec, implicit-def dead %scc, implicit %exec
|
||||
S_ENDPGM
|
||||
|
||||
...
|
||||
|
|
@ -400,9 +400,9 @@ store_label:
|
|||
|
||||
; Check that "pulling out" SDWA operands works correctly.
|
||||
; GCN-LABEL: {{^}}pulled_out_test:
|
||||
; NOSDWA-DAG: v_and_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
|
||||
; NOSDWA-DAG: v_and_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
|
||||
; NOSDWA-DAG: v_lshlrev_b16_e32 v{{[0-9]+}}, 8, v{{[0-9]+}}
|
||||
; NOSDWA-DAG: v_and_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
|
||||
; NOSDWA-DAG: v_and_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
|
||||
; NOSDWA-DAG: v_lshlrev_b16_e32 v{{[0-9]+}}, 8, v{{[0-9]+}}
|
||||
; NOSDWA: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
|
||||
; NOSDWA-NOT: v_and_b32_sdwa
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@ define amdgpu_kernel void @s_sint_to_fp_i64_to_f16(half addrspace(1)* %out, i64
|
|||
; GCN: v_cndmask
|
||||
|
||||
; GCN-DAG: v_cmp_eq_u64
|
||||
; GCN-DAG: v_cmp_lt_u64
|
||||
; GCN-DAG: v_cmp_gt_u64
|
||||
|
||||
; GCN: v_xor_b32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}}
|
||||
; GCN: v_cndmask_b32_e{{32|64}} [[SIGN_SEL:v[0-9]+]],
|
||||
|
|
@ -57,7 +57,7 @@ define amdgpu_kernel void @s_sint_to_fp_i64_to_f32(float addrspace(1)* %out, i64
|
|||
; GCN: v_cndmask
|
||||
|
||||
; GCN-DAG: v_cmp_eq_u64
|
||||
; GCN-DAG: v_cmp_lt_u64
|
||||
; GCN-DAG: v_cmp_gt_u64
|
||||
|
||||
; GCN: v_xor_b32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}}
|
||||
; GCN: v_cndmask_b32_e{{32|64}} [[SIGN_SEL:v[0-9]+]],
|
||||
|
|
|
|||
|
|
@ -19,7 +19,7 @@ define amdgpu_kernel void @s_uint_to_fp_i64_to_f16(half addrspace(1)* %out, i64
|
|||
; GCN: v_cndmask
|
||||
|
||||
; GCN-DAG: v_cmp_eq_u64
|
||||
; GCN-DAG: v_cmp_lt_u64
|
||||
; GCN-DAG: v_cmp_gt_u64
|
||||
|
||||
; GCN: v_add_i32_e32 [[VR:v[0-9]+]]
|
||||
; GCN: v_cvt_f16_f32_e32 [[VR_F16:v[0-9]+]], [[VR]]
|
||||
|
|
@ -50,7 +50,7 @@ define amdgpu_kernel void @s_uint_to_fp_i64_to_f32(float addrspace(1)* %out, i64
|
|||
; GCN: v_cndmask
|
||||
|
||||
; GCN-DAG: v_cmp_eq_u64
|
||||
; GCN-DAG: v_cmp_lt_u64
|
||||
; GCN-DAG: v_cmp_gt_u64
|
||||
|
||||
; GCN: v_add_i32_e32 [[VR:v[0-9]+]]
|
||||
; GCN: {{buffer|flat}}_store_dword {{.*}}[[VR]]
|
||||
|
|
|
|||
Loading…
Reference in New Issue