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R600/SI: Use the same names for VOP3 operands and encoding fields 

This makes it possible to reorder the operands without breaking the
encoding.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182283
This commit is contained in:
Tom Stellard 2013-05-20 15:02:08 +00:00
parent b35efba4d9
commit 459a79a81c
2 changed files with 36 additions and 36 deletions
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60
llvm/lib/Target/R600/SIInstrFormats.td
View File

@ -185,25 +185,25 @@ class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> :
class VOP3 <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
Enc64 <outs, ins, asm, pattern> {
bits<8> VDST;
bits<9> SRC0;
bits<9> SRC1;
bits<9> SRC2;
bits<3> ABS;
bits<1> CLAMP;
bits<2> OMOD;
bits<3> NEG;
bits<8> dst;
bits<9> src0;
bits<9> src1;
bits<9> src2;
bits<3> abs;
bits<1> clamp;
bits<2> omod;
bits<3> neg;
let Inst{7-0} = VDST;
let Inst{10-8} = ABS;
let Inst{11} = CLAMP;
let Inst{7-0} = dst;
let Inst{10-8} = abs;
let Inst{11} = clamp;
let Inst{25-17} = op;
let Inst{31-26} = 0x34; //encoding
let Inst{40-32} = SRC0;
let Inst{49-41} = SRC1;
let Inst{58-50} = SRC2;
let Inst{60-59} = OMOD;
let Inst{63-61} = NEG;
let Inst{40-32} = src0;
let Inst{49-41} = src1;
let Inst{58-50} = src2;
let Inst{60-59} = omod;
let Inst{63-61} = neg;
let mayLoad = 0;
let mayStore = 0;
@ -213,23 +213,23 @@ class VOP3 <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
class VOP3b <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
Enc64 <outs, ins, asm, pattern> {
bits<8> VDST;
bits<9> SRC0;
bits<9> SRC1;
bits<9> SRC2;
bits<7> SDST;
bits<2> OMOD;
bits<3> NEG;
bits<8> dst;
bits<9> src0;
bits<9> src1;
bits<9> src2;
bits<7> sdst;
bits<2> omod;
bits<3> neg;
let Inst{7-0} = VDST;
let Inst{14-8} = SDST;
let Inst{7-0} = dst;
let Inst{14-8} = sdst;
let Inst{25-17} = op;
let Inst{31-26} = 0x34; //encoding
let Inst{40-32} = SRC0;
let Inst{49-41} = SRC1;
let Inst{58-50} = SRC2;
let Inst{60-59} = OMOD;
let Inst{63-61} = NEG;
let Inst{40-32} = src0;
let Inst{49-41} = src1;
let Inst{58-50} = src2;
let Inst{60-59} = omod;
let Inst{63-61} = neg;
let mayLoad = 0;
let mayStore = 0;

12
llvm/lib/Target/R600/SIInstrInfo.td
View File

@ -163,8 +163,8 @@ multiclass VOP1_Helper <bits<8> op, RegisterClass drc, RegisterClass src,
i32imm:$omod, i32imm:$neg),
opName#"_e64 $dst, $src0, $abs, $clamp, $omod, $neg", []
>, VOP <opName> {
let SRC1 = SIOperand.ZERO;
let SRC2 = SIOperand.ZERO;
let src1 = SIOperand.ZERO;
let src2 = SIOperand.ZERO;
}
}
@ -189,7 +189,7 @@ multiclass VOP2_Helper <bits<6> op, RegisterClass vrc, RegisterClass arc,
i32imm:$omod, i32imm:$neg),
opName#"_e64 $dst, $src0, $src1, $abs, $clamp, $omod, $neg", []
>, VOP <opName>, VOP2_REV<revOp#"_e64", !eq(revOp, opName)> {
let SRC2 = SIOperand.ZERO;
let src2 = SIOperand.ZERO;
}
}
@ -217,11 +217,11 @@ multiclass VOP2b_32 <bits<6> op, string opName, list<dag> pattern,
i32imm:$omod, i32imm:$neg),
opName#"_e64 $dst, $src0, $src1, $abs, $clamp, $omod, $neg", []
>, VOP <opName>, VOP2_REV<revOp#"_e64", !eq(revOp, opName)> {
let SRC2 = SIOperand.ZERO;
let src2 = SIOperand.ZERO;
/* the VOP2 variant puts the carry out into VCC, the VOP3 variant
can write it into any SGPR. We currently don't use the carry out,
so for now hardcode it to VCC as well */
let SDST = SIOperand.VCC;
let sdst = SIOperand.VCC;
}
}
@ -244,7 +244,7 @@ multiclass VOPC_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
[(set SReg_64:$dst, (i1 (setcc (vt arc:$src0), arc:$src1, cond)))]
)
>, VOP <opName> {
let SRC2 = SIOperand.ZERO;
let src2 = SIOperand.ZERO;
}
}