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Revert "This pass, fixing an erratum in some LEON 2 processors..." 

Summary:
Reading Atmel's AT697E errata document this does not seem like a valid
workaround. While the text only mentions SDIV, it says that the ICC flags
can be wrong, and those are only generated by SDIVcc. Verification on
hardware shows that simply replacing SDIV with SDIVcc does not avoid
the bug with negative operands.

This reverts r283727.

Reviewers: lero_chris, jyknight

Reviewed By: jyknight

Subscribers: fedor.sergeev, jrtc27, llvm-commits

Differential Revision: https://reviews.llvm.org/D45813

llvm-svn: 330397
This commit is contained in:
Daniel Cederman 2018-04-20 07:53:27 +00:00
parent c67b3ffba7
commit 4557178061
6 changed files with 1 additions and 29 deletions
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8
llvm/lib/Target/Sparc/LeonFeatures.td
View File

@ -37,14 +37,6 @@ def LeonCASA : SubtargetFeature<
"Enable CASA instruction for LEON3 and LEON4 processors"
>;
def ReplaceSDIV : SubtargetFeature<
"replacesdiv",
"PerformSDIVReplace",
"true",
"AT697E erratum fix: Do not emit SDIV, emit SDIVCC instead"
>;
def InsertNOPLoad: SubtargetFeature<
"insertnopload",
"InsertNOPLoad",

2
llvm/lib/Target/Sparc/Sparc.td
View File

@ -130,7 +130,7 @@ def : Processor<"leon2", LEON2Itineraries,
// LEON 2 FT (AT697E)
// TO DO: Place-holder: Processor specific features will be added *very* soon here.
def : Processor<"at697e", LEON2Itineraries,
[FeatureLeon, ReplaceSDIV, InsertNOPLoad]>;
[FeatureLeon, InsertNOPLoad]>;
// LEON 2 FT (AT697F)
// TO DO: Place-holder: Processor specific features will be added *very* soon here.

6
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
View File

@ -362,12 +362,6 @@ void SparcDAGToDAGISel::Select(SDNode *N) {
// FIXME: Handle div by immediate.
unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
// SDIV is a hardware erratum on some LEON2 processors. Replace it with SDIVcc here.
if (((SparcTargetMachine&)TM).getSubtargetImpl()->performSDIVReplace()
&&
Opcode == SP::SDIVrr) {
Opcode = SP::SDIVCCrr;
}
CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart);
return;
}

1
llvm/lib/Target/Sparc/SparcSubtarget.cpp
View File

@ -44,7 +44,6 @@ SparcSubtarget &SparcSubtarget::initializeSubtargetDependencies(StringRef CPU,
// Leon features
HasLeonCasa = false;
HasUmacSmac = false;
PerformSDIVReplace = false;
InsertNOPLoad = false;
FixAllFDIVSQRT = false;
DetectRoundChange = false;

2
llvm/lib/Target/Sparc/SparcSubtarget.h
View File

@ -50,7 +50,6 @@ class SparcSubtarget : public SparcGenSubtargetInfo {
bool InsertNOPLoad;
bool FixAllFDIVSQRT;
bool DetectRoundChange;
bool PerformSDIVReplace;
SparcInstrInfo InstrInfo;
SparcTargetLowering TLInfo;
@ -92,7 +91,6 @@ public:
// Leon options
bool hasUmacSmac() const { return HasUmacSmac; }
bool performSDIVReplace() const { return PerformSDIVReplace; }
bool hasLeonCasa() const { return HasLeonCasa; }
bool insertNOPLoad() const { return InsertNOPLoad; }
bool fixAllFDIVSQRT() const { return FixAllFDIVSQRT; }

11
llvm/test/CodeGen/SPARC/LeonReplaceSDIVPassUT.ll
View File

@ -1,11 +0,0 @@
; RUN: llc %s -O0 -march=sparc -o - | FileCheck %s -check-prefix=NO_REPLACE_SDIV
; RUN: llc %s -O0 -march=sparc -mcpu=at697e -o - | FileCheck %s -check-prefix=REPLACE_SDIV
; REPLACE_SDIV: sdivcc %o0, %o1, %o0
; NO_REPLACE_SDIV: sdiv %o0, %o1, %o0
define i32 @lbr59(i32 %a, i32 %b)
{
%r = sdiv i32 %a, %b
ret i32 %r
}