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[X86][NFC] Add a `use-aa` feature. 

Summary:
This allows enabling useaa on the command-line and will allow enabling the
feature on a per-CPU basis where benchmarking shows improvements.

This is modelled after the ARM/AArch64 target.

Reviewers: RKSimon, andreadb, craig.topper

Subscribers: javed.absar, kristof.beyls, hiraditya, ychen, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67266

llvm-svn: 371989
This commit is contained in:
Clement Courbet 2019-09-16 14:05:28 +00:00
parent f201b1c918
commit 44bfbcc28e
2 changed files with 8 additions and 0 deletions
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4
llvm/lib/Target/X86/X86.td
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@ -457,6 +457,10 @@ def FeatureMergeToThreeWayBranch : SubtargetFeature<"merge-to-threeway-branch",
"Merge branches to a three-way " "Merge branches to a three-way "
"conditional branch">; "conditional branch">;
// Enable use of alias analysis during code generation.
def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true",
"Use alias analysis during codegen">;
// Bonnell // Bonnell
def ProcIntelAtom : SubtargetFeature<"", "X86ProcFamily", "IntelAtom", "">; def ProcIntelAtom : SubtargetFeature<"", "X86ProcFamily", "IntelAtom", "">;
// Silvermont // Silvermont

4
llvm/lib/Target/X86/X86Subtarget.h
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@ -427,6 +427,9 @@ protected:
/// Use software floating point for code generation. /// Use software floating point for code generation.
bool UseSoftFloat = false; bool UseSoftFloat = false;
/// Use alias analysis during code generation.
bool UseAA = false;
/// The minimum alignment known to hold of the stack frame on /// The minimum alignment known to hold of the stack frame on
/// entry to the function and which must be maintained by every function. /// entry to the function and which must be maintained by every function.
unsigned stackAlignment = 4; unsigned stackAlignment = 4;
@ -741,6 +744,7 @@ public:
X86ProcFamily == IntelTRM; X86ProcFamily == IntelTRM;
} }
bool useSoftFloat() const { return UseSoftFloat; } bool useSoftFloat() const { return UseSoftFloat; }
bool useAA() const override { return UseAA; }
/// Use mfence if we have SSE2 or we're on x86-64 (even if we asked for /// Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
/// no-sse2). There isn't any reason to disable it if the target processor /// no-sse2). There isn't any reason to disable it if the target processor