[mips] Interrupt attribute support for mips32r2+.
Summary: This patch adds support for using the "interrupt" attribute on Mips for interrupt handling functions. At this time only mips32r2+ with the o32 ABI with the static relocation model is supported. Unsupported configurations will be rejected Patch by Simon Dardis (+ clang-format & some trivial changes to follow the LLVM coding standards by me). Reviewers: mpf, dsanders Subscribers: dsanders, vkalintiris, llvm-commits Differential Revision: http://reviews.llvm.org/D10768 llvm-svn: 251286
This commit is contained in:
Vasileios Kalintiris
parent
684af8156c
commit
43dff0c033
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@ -427,3 +427,28 @@ def CSR_Mips16RetHelper :
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CalleeSavedRegs<(add V0, V1, FP,
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(sequence "A%u", 3, 0), (sequence "S%u", 7, 0),
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(sequence "D%u", 15, 10))>;
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def CSR_Interrupt_32R6 : CalleeSavedRegs<(add (sequence "A%u", 3, 0),
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(sequence "S%u", 7, 0),
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(sequence "V%u", 1, 0),
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(sequence "T%u", 9, 0),
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RA, FP, GP, AT)>;
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def CSR_Interrupt_32 : CalleeSavedRegs<(add (sequence "A%u", 3, 0),
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(sequence "S%u", 7, 0),
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(sequence "V%u", 1, 0),
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(sequence "T%u", 9, 0),
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RA, FP, GP, AT, LO0, HI0)>;
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def CSR_Interrupt_64R6 : CalleeSavedRegs<(add (sequence "A%u_64", 3, 0),
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(sequence "V%u_64", 1, 0),
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(sequence "S%u_64", 7, 0),
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(sequence "T%u_64", 9, 0),
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RA_64, FP_64, GP_64, AT_64)>;
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def CSR_Interrupt_64 : CalleeSavedRegs<(add (sequence "A%u_64", 3, 0),
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(sequence "S%u_64", 7, 0),
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(sequence "T%u_64", 9, 0),
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(sequence "V%u_64", 1, 0),
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RA_64, FP_64, GP_64, AT_64,
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LO0_64, HI0_64)>;
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@ -117,6 +117,7 @@ const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
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case MipsISD::GPRel: return "MipsISD::GPRel";
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case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer";
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case MipsISD::Ret: return "MipsISD::Ret";
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case MipsISD::ERet: return "MipsISD::ERet";
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case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN";
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case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
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case MipsISD::FPCmp: return "MipsISD::FPCmp";
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@ -2948,8 +2949,12 @@ MipsTargetLowering::LowerFormalArguments(SDValue Chain,
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MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
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*DAG.getContext());
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CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1);
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Function::const_arg_iterator FuncArg =
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DAG.getMachineFunction().getFunction()->arg_begin();
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const Function *Func = DAG.getMachineFunction().getFunction();
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Function::const_arg_iterator FuncArg = Func->arg_begin();
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if (Func->hasFnAttribute("interrupt"))
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assert(Func->arg_empty() &&
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"Functions with the interrupt attribute cannot have arguments!");
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CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg);
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MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(),
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@ -3101,8 +3106,20 @@ MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const
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}
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SDValue
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MipsTargetLowering::LowerReturn(SDValue Chain,
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CallingConv::ID CallConv, bool IsVarArg,
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MipsTargetLowering::LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
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SDLoc DL, SelectionDAG &DAG) const {
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MachineFunction &MF = DAG.getMachineFunction();
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MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
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MipsFI->setISR();
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return DAG.getNode(MipsISD::ERet, DL, MVT::Other, RetOps);
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}
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SDValue
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MipsTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
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bool IsVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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SDLoc DL, SelectionDAG &DAG) const {
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@ -3195,7 +3212,11 @@ MipsTargetLowering::LowerReturn(SDValue Chain,
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if (Flag.getNode())
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RetOps.push_back(Flag);
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// Return on Mips is always a "jr $ra"
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// ISRs must use "eret".
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if (DAG.getMachineFunction().getFunction()->hasFnAttribute("interrupt"))
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return LowerInterruptReturn(RetOps, DL, DAG);
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// Standard return on Mips is a "jr $ra"
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return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps);
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}
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@ -67,6 +67,10 @@ namespace llvm {
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// Return
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Ret,
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// Interrupt, exception, error trap Return
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ERet,
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// Software Exception Return.
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EH_RETURN,
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// Node used to extract integer from accumulator.
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@ -482,6 +486,9 @@ namespace llvm {
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const SmallVectorImpl<SDValue> &OutVals,
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SDLoc dl, SelectionDAG &DAG) const override;
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SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps, SDLoc DL,
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SelectionDAG &DAG) const;
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bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override;
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// Inline asm support
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@ -77,6 +77,9 @@ def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
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def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
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[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
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def MipsERet : SDNode<"MipsISD::ERet", SDTNone,
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[SDNPHasChain, SDNPOptInGlue, SDNPSideEffect]>;
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// These are target-independent nodes, but have target-specific formats.
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def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
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[SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
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@ -1146,6 +1149,9 @@ class TrapBase<Instruction RealInst>
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let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
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def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
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let isReturn=1, isTerminator=1, isBarrier=1, hasCtrlDep=1, hasSideEffects=1 in
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def ERet : PseudoSE<(outs), (ins), [(MipsERet)]>;
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let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
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def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
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[(callseq_start timm:$amt)]>;
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@ -75,11 +75,26 @@ void MipsFunctionInfo::createEhDataRegsFI() {
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}
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}
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void MipsFunctionInfo::createISRRegFI() {
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// ISRs require spill slots for Status & ErrorPC Coprocessor 0 registers.
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// The current implementation only supports Mips32r2+ not Mips64rX. Status
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// is always 32 bits, ErrorPC is 32 or 64 bits dependant on architecture,
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// however Mips32r2+ is the supported architecture.
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const TargetRegisterClass *RC = &Mips::GPR32RegClass;
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for (int I = 0; I < 2; ++I)
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ISRDataRegFI[I] = MF.getFrameInfo()->CreateStackObject(
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RC->getSize(), RC->getAlignment(), false);
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}
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bool MipsFunctionInfo::isEhDataRegFI(int FI) const {
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return CallsEhReturn && (FI == EhDataRegFI[0] || FI == EhDataRegFI[1]
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|| FI == EhDataRegFI[2] || FI == EhDataRegFI[3]);
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}
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bool MipsFunctionInfo::isISRRegFI(int FI) const {
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return IsISR && (FI == ISRDataRegFI[0] || FI == ISRDataRegFI[1]);
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}
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MachinePointerInfo MipsFunctionInfo::callPtrInfo(const char *ES) {
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return MachinePointerInfo(MF.getPSVManager().getExternalSymbolCallEntry(ES));
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}
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@ -34,7 +34,7 @@ class MipsFunctionInfo : public MachineFunctionInfo {
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public:
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MipsFunctionInfo(MachineFunction &MF)
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: MF(MF), SRetReturnReg(0), GlobalBaseReg(0), Mips16SPAliasReg(0),
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VarArgsFrameIndex(0), CallsEhReturn(false), SaveS2(false),
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VarArgsFrameIndex(0), CallsEhReturn(false), IsISR(false), SaveS2(false),
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MoveF64ViaSpillFI(-1) {}
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~MipsFunctionInfo();
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@ -70,6 +70,14 @@ public:
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/// object representing a GOT entry for an external function.
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MachinePointerInfo callPtrInfo(const char *ES);
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// Functions with the "interrupt" attribute require special prologues,
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// epilogues and additional spill slots.
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bool isISR() const { return IsISR; }
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void setISR() { IsISR = true; }
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void createISRRegFI();
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int getISRRegFI(unsigned Reg) const { return ISRDataRegFI[Reg]; }
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bool isISRRegFI(int FI) const;
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/// Create a MachinePointerInfo that has a GlobalValuePseudoSourceValue object
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/// representing a GOT entry for a global function.
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MachinePointerInfo callPtrInfo(const GlobalValue *GV);
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@ -116,6 +124,12 @@ private:
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/// Frame objects for spilling eh data registers.
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int EhDataRegFI[4];
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/// ISR - Whether the function is an Interrupt Service Routine.
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bool IsISR;
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/// Frame objects for spilling C0_STATUS, C0_EPC
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int ISRDataRegFI[2];
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// saveS2
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bool SaveS2;
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@ -84,6 +84,16 @@ MipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
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const MCPhysReg *
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MipsRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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const MipsSubtarget &Subtarget = MF->getSubtarget<MipsSubtarget>();
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const Function *F = MF->getFunction();
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if (F->hasFnAttribute("interrupt")) {
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if (Subtarget.hasMips64())
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return Subtarget.hasMips64r6() ? CSR_Interrupt_64R6_SaveList
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: CSR_Interrupt_64_SaveList;
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else
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return Subtarget.hasMips32r6() ? CSR_Interrupt_32R6_SaveList
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: CSR_Interrupt_32_SaveList;
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}
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if (Subtarget.isSingleFloat())
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return CSR_SingleFloatOnly_SaveList;
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@ -17,6 +17,7 @@
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#include "MipsMachineFunction.h"
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#include "MipsSEInstrInfo.h"
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#include "MipsSubtarget.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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@ -415,6 +416,9 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF,
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BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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if (MF.getFunction()->hasFnAttribute("interrupt"))
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emitInterruptPrologueStub(MF, MBB);
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const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
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if (CSI.size()) {
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@ -530,6 +534,135 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF,
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}
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}
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void MipsSEFrameLowering::emitInterruptPrologueStub(
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MachineFunction &MF, MachineBasicBlock &MBB) const {
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MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
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MachineBasicBlock::iterator MBBI = MBB.begin();
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DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
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// Report an error the target doesn't support Mips32r2 or later.
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// The epilogue relies on the use of the "ehb" to clear execution
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// hazards. Pre R2 Mips relies on an implementation defined number
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// of "ssnop"s to clear the execution hazard. Support for ssnop hazard
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// clearing is not provided so reject that configuration.
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if (!STI.hasMips32r2())
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report_fatal_error(
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"\"interrupt\" attribute is not supported on pre-r2 MIPS or"
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"Mips16 targets.");
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// The GP register contains the "user" value, so we cannot perform
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// any gp relative loads until we restore the "kernel" or "system" gp
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// value. Until support is written we shall only accept the static
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// relocation model.
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if ((STI.getRelocationModel() != Reloc::Static))
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report_fatal_error("\"interrupt\" attribute is only supported for the "
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"static relocation model on MIPS at the present time.");
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if (!STI.isABI_O32() || STI.hasMips64())
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report_fatal_error("\"interrupt\" attribute is only supported for the "
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"O32 ABI on MIPS32r2+ at the present time.");
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// Perform ISR handling like GCC
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StringRef IntKind =
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MF.getFunction()->getFnAttribute("interrupt").getValueAsString();
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const TargetRegisterClass *PtrRC = &Mips::GPR32RegClass;
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// EIC interrupt handling needs to read the Cause register to disable
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// interrupts.
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if (IntKind == "eic") {
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// Coprocessor registers are always live per se.
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MBB.addLiveIn(Mips::COP013);
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BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K0)
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.addReg(Mips::COP013)
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.addImm(0)
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.setMIFlag(MachineInstr::FrameSetup);
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BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::EXT), Mips::K0)
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.addReg(Mips::K0)
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.addImm(10)
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.addImm(6)
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.setMIFlag(MachineInstr::FrameSetup);
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}
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// Fetch and spill EPC
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MBB.addLiveIn(Mips::COP014);
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BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K1)
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.addReg(Mips::COP014)
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.addImm(0)
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.setMIFlag(MachineInstr::FrameSetup);
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STI.getInstrInfo()->storeRegToStack(MBB, MBBI, Mips::K1, false,
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MipsFI->getISRRegFI(0), PtrRC,
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STI.getRegisterInfo(), 0);
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// Fetch and Spill Status
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MBB.addLiveIn(Mips::COP012);
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BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K1)
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.addReg(Mips::COP012)
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.addImm(0)
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.setMIFlag(MachineInstr::FrameSetup);
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STI.getInstrInfo()->storeRegToStack(MBB, MBBI, Mips::K1, false,
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MipsFI->getISRRegFI(1), PtrRC,
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STI.getRegisterInfo(), 0);
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// Build the configuration for disabling lower priority interrupts. Non EIC
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// interrupts need to be masked off with zero, EIC from the Cause register.
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unsigned InsPosition = 8;
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unsigned InsSize = 0;
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unsigned SrcReg = Mips::ZERO;
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// If the interrupt we're tied to is the EIC, switch the source for the
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// masking off interrupts to the cause register.
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if (IntKind == "eic") {
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SrcReg = Mips::K0;
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InsPosition = 10;
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InsSize = 6;
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} else
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InsSize = StringSwitch<unsigned>(IntKind)
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.Case("sw0", 1)
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.Case("sw1", 2)
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.Case("hw0", 3)
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.Case("hw1", 4)
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.Case("hw2", 5)
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.Case("hw3", 6)
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.Case("hw4", 7)
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.Case("hw5", 8)
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.Default(0);
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assert(InsSize != 0 && "Unknown interrupt type!");
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BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1)
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.addReg(SrcReg)
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.addImm(InsPosition)
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.addImm(InsSize)
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.addReg(Mips::K1)
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.setMIFlag(MachineInstr::FrameSetup);
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// Mask off KSU, ERL, EXL
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BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1)
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.addReg(Mips::ZERO)
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.addImm(1)
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.addImm(4)
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.addReg(Mips::K1)
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.setMIFlag(MachineInstr::FrameSetup);
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// Disable the FPU as we are not spilling those register sets.
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if (!STI.useSoftFloat())
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BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1)
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.addReg(Mips::ZERO)
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.addImm(29)
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.addImm(1)
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.addReg(Mips::K1)
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.setMIFlag(MachineInstr::FrameSetup);
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// Set the new status
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BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP012)
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.addReg(Mips::K1)
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.addImm(0)
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.setMIFlag(MachineInstr::FrameSetup);
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}
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void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
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@ -541,7 +674,7 @@ void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF,
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const MipsRegisterInfo &RegInfo =
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*static_cast<const MipsRegisterInfo *>(STI.getRegisterInfo());
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DebugLoc dl = MBBI->getDebugLoc();
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DebugLoc DL = MBBI->getDebugLoc();
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MipsABIInfo ABI = STI.getABI();
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unsigned SP = ABI.GetStackPtr();
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unsigned FP = ABI.GetFramePtr();
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@ -557,7 +690,7 @@ void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF,
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--I;
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// Insert instruction "move $sp, $fp" at this location.
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BuildMI(MBB, I, dl, TII.get(MOVE), SP).addReg(FP).addReg(ZERO);
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BuildMI(MBB, I, DL, TII.get(MOVE), SP).addReg(FP).addReg(ZERO);
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}
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if (MipsFI->callsEhReturn()) {
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|
|
@ -576,6 +709,9 @@ void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF,
|
|||
}
|
||||
}
|
||||
|
||||
if (MF.getFunction()->hasFnAttribute("interrupt"))
|
||||
emitInterruptEpilogueStub(MF, MBB);
|
||||
|
||||
// Get the number of bytes from FrameInfo
|
||||
uint64_t StackSize = MFI->getStackSize();
|
||||
|
||||
|
|
@ -586,6 +722,37 @@ void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF,
|
|||
TII.adjustStackPtr(SP, StackSize, MBB, MBBI);
|
||||
}
|
||||
|
||||
void MipsSEFrameLowering::emitInterruptEpilogueStub(
|
||||
MachineFunction &MF, MachineBasicBlock &MBB) const {
|
||||
|
||||
MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
|
||||
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
|
||||
DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
|
||||
|
||||
// Perform ISR handling like GCC
|
||||
const TargetRegisterClass *PtrRC = &Mips::GPR32RegClass;
|
||||
|
||||
// Disable Interrupts.
|
||||
BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::DI), Mips::ZERO);
|
||||
BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::EHB));
|
||||
|
||||
// Restore EPC
|
||||
STI.getInstrInfo()->loadRegFromStackSlot(MBB, MBBI, Mips::K1,
|
||||
MipsFI->getISRRegFI(0), PtrRC,
|
||||
STI.getRegisterInfo());
|
||||
BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP014)
|
||||
.addReg(Mips::K1)
|
||||
.addImm(0);
|
||||
|
||||
// Restore Status
|
||||
STI.getInstrInfo()->loadRegFromStackSlot(MBB, MBBI, Mips::K1,
|
||||
MipsFI->getISRRegFI(1), PtrRC,
|
||||
STI.getRegisterInfo());
|
||||
BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP012)
|
||||
.addReg(Mips::K1)
|
||||
.addImm(0);
|
||||
}
|
||||
|
||||
bool MipsSEFrameLowering::
|
||||
spillCalleeSavedRegisters(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator MI,
|
||||
|
|
@ -607,6 +774,26 @@ spillCalleeSavedRegisters(MachineBasicBlock &MBB,
|
|||
if (!IsRAAndRetAddrIsTaken)
|
||||
EntryBlock->addLiveIn(Reg);
|
||||
|
||||
// ISRs require HI/LO to be spilled into kernel registers to be then
|
||||
// spilled to the stack frame.
|
||||
bool IsLOHI = (Reg == Mips::LO0 || Reg == Mips::LO0_64 ||
|
||||
Reg == Mips::HI0 || Reg == Mips::HI0_64);
|
||||
const Function *Func = MBB.getParent()->getFunction();
|
||||
if (IsLOHI && Func->hasFnAttribute("interrupt")) {
|
||||
DebugLoc DL = MI->getDebugLoc();
|
||||
|
||||
unsigned Op = 0;
|
||||
if (!STI.getABI().ArePtrs64bit()) {
|
||||
Op = (Reg == Mips::HI0) ? Mips::MFHI : Mips::MFLO;
|
||||
Reg = Mips::K0;
|
||||
} else {
|
||||
Op = (Reg == Mips::HI0) ? Mips::MFHI64 : Mips::MFLO64;
|
||||
Reg = Mips::K0_64;
|
||||
}
|
||||
BuildMI(MBB, MI, DL, TII.get(Op), Mips::K0)
|
||||
.setMIFlag(MachineInstr::FrameSetup);
|
||||
}
|
||||
|
||||
// Insert the spill to the stack frame.
|
||||
bool IsKill = !IsRAAndRetAddrIsTaken;
|
||||
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
|
||||
|
|
@ -657,6 +844,10 @@ void MipsSEFrameLowering::determineCalleeSaves(MachineFunction &MF,
|
|||
if (MipsFI->callsEhReturn())
|
||||
MipsFI->createEhDataRegsFI();
|
||||
|
||||
// Create spill slots for Coprocessor 0 registers if function is an ISR.
|
||||
if (MipsFI->isISR())
|
||||
MipsFI->createISRRegFI();
|
||||
|
||||
// Expand pseudo instructions which load, store or copy accumulators.
|
||||
// Add an emergency spill slot if a pseudo was expanded.
|
||||
if (ExpandPseudo(MF).expand()) {
|
||||
|
|
|
|||
|
|
@ -37,8 +37,13 @@ public:
|
|||
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
|
||||
RegScavenger *RS) const override;
|
||||
unsigned ehDataReg(unsigned I) const;
|
||||
};
|
||||
|
||||
private:
|
||||
void emitInterruptEpilogueStub(MachineFunction &MF,
|
||||
MachineBasicBlock &MBB) const;
|
||||
void emitInterruptPrologueStub(MachineFunction &MF,
|
||||
MachineBasicBlock &MBB) const;
|
||||
};
|
||||
} // End llvm namespace
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1181,6 +1181,10 @@ bool MipsSETargetLowering::isEligibleForTailCallOptimization(
|
|||
if (!EnableMipsTailCalls)
|
||||
return false;
|
||||
|
||||
// Exception has to be cleared with eret.
|
||||
if (FI.isISR())
|
||||
return false;
|
||||
|
||||
// Return false if either the callee or caller has a byval argument.
|
||||
if (CCInfo.getInRegsParamsCount() > 0 || FI.hasByvalArg())
|
||||
return false;
|
||||
|
|
|
|||
|
|
@ -212,6 +212,33 @@ storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
|||
Opc = Mips::ST_W;
|
||||
else if (RC->hasType(MVT::v2i64) || RC->hasType(MVT::v2f64))
|
||||
Opc = Mips::ST_D;
|
||||
else if (Mips::LO32RegClass.hasSubClassEq(RC))
|
||||
Opc = Mips::SW;
|
||||
else if (Mips::LO64RegClass.hasSubClassEq(RC))
|
||||
Opc = Mips::SD;
|
||||
else if (Mips::HI32RegClass.hasSubClassEq(RC))
|
||||
Opc = Mips::SW;
|
||||
else if (Mips::HI64RegClass.hasSubClassEq(RC))
|
||||
Opc = Mips::SD;
|
||||
|
||||
// Hi, Lo are normally caller save but they are callee save
|
||||
// for interrupt handling.
|
||||
const Function *Func = MBB.getParent()->getFunction();
|
||||
if (Func->hasFnAttribute("interrupt")) {
|
||||
if (Mips::HI32RegClass.hasSubClassEq(RC)) {
|
||||
BuildMI(MBB, I, DL, get(Mips::MFHI), Mips::K0);
|
||||
SrcReg = Mips::K0;
|
||||
} else if (Mips::HI64RegClass.hasSubClassEq(RC)) {
|
||||
BuildMI(MBB, I, DL, get(Mips::MFHI64), Mips::K0_64);
|
||||
SrcReg = Mips::K0_64;
|
||||
} else if (Mips::LO32RegClass.hasSubClassEq(RC)) {
|
||||
BuildMI(MBB, I, DL, get(Mips::MFLO), Mips::K0);
|
||||
SrcReg = Mips::K0;
|
||||
} else if (Mips::LO64RegClass.hasSubClassEq(RC)) {
|
||||
BuildMI(MBB, I, DL, get(Mips::MFLO64), Mips::K0_64);
|
||||
SrcReg = Mips::K0_64;
|
||||
}
|
||||
}
|
||||
|
||||
assert(Opc && "Register class not handled!");
|
||||
BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
|
||||
|
|
@ -227,6 +254,11 @@ loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
|||
MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
|
||||
unsigned Opc = 0;
|
||||
|
||||
const Function *Func = MBB.getParent()->getFunction();
|
||||
bool ReqIndirectLoad = Func->hasFnAttribute("interrupt") &&
|
||||
(DestReg == Mips::LO0 || DestReg == Mips::LO0_64 ||
|
||||
DestReg == Mips::HI0 || DestReg == Mips::HI0_64);
|
||||
|
||||
if (Mips::GPR32RegClass.hasSubClassEq(RC))
|
||||
Opc = Mips::LW;
|
||||
else if (Mips::GPR64RegClass.hasSubClassEq(RC))
|
||||
|
|
@ -253,10 +285,44 @@ loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
|||
Opc = Mips::LD_W;
|
||||
else if (RC->hasType(MVT::v2i64) || RC->hasType(MVT::v2f64))
|
||||
Opc = Mips::LD_D;
|
||||
else if (Mips::HI32RegClass.hasSubClassEq(RC))
|
||||
Opc = Mips::LW;
|
||||
else if (Mips::HI64RegClass.hasSubClassEq(RC))
|
||||
Opc = Mips::LD;
|
||||
else if (Mips::LO32RegClass.hasSubClassEq(RC))
|
||||
Opc = Mips::LW;
|
||||
else if (Mips::LO64RegClass.hasSubClassEq(RC))
|
||||
Opc = Mips::LD;
|
||||
|
||||
assert(Opc && "Register class not handled!");
|
||||
BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset)
|
||||
.addMemOperand(MMO);
|
||||
|
||||
if (!ReqIndirectLoad)
|
||||
BuildMI(MBB, I, DL, get(Opc), DestReg)
|
||||
.addFrameIndex(FI)
|
||||
.addImm(Offset)
|
||||
.addMemOperand(MMO);
|
||||
else {
|
||||
// Load HI/LO through K0. Notably the DestReg is encoded into the
|
||||
// instruction itself.
|
||||
unsigned Reg = Mips::K0;
|
||||
unsigned LdOp = Mips::MTLO;
|
||||
if (DestReg == Mips::HI0)
|
||||
LdOp = Mips::MTHI;
|
||||
|
||||
if (Subtarget.getABI().ArePtrs64bit()) {
|
||||
Reg = Mips::K0_64;
|
||||
if (DestReg == Mips::HI0_64)
|
||||
LdOp = Mips::MTHI64;
|
||||
else
|
||||
LdOp = Mips::MTLO64;
|
||||
}
|
||||
|
||||
BuildMI(MBB, I, DL, get(Opc), Reg)
|
||||
.addFrameIndex(FI)
|
||||
.addImm(Offset)
|
||||
.addMemOperand(MMO);
|
||||
BuildMI(MBB, I, DL, get(LdOp)).addReg(Reg);
|
||||
}
|
||||
}
|
||||
|
||||
bool MipsSEInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
|
||||
|
|
@ -270,6 +336,9 @@ bool MipsSEInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
|
|||
case Mips::RetRA:
|
||||
expandRetRA(MBB, MI);
|
||||
break;
|
||||
case Mips::ERet:
|
||||
expandERet(MBB, MI);
|
||||
break;
|
||||
case Mips::PseudoMFHI:
|
||||
Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI;
|
||||
expandPseudoMFHiLo(MBB, MI, Opc);
|
||||
|
|
@ -437,6 +506,11 @@ void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB,
|
|||
BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn)).addReg(Mips::RA);
|
||||
}
|
||||
|
||||
void MipsSEInstrInfo::expandERet(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator I) const {
|
||||
BuildMI(MBB, I, I->getDebugLoc(), get(Mips::ERET));
|
||||
}
|
||||
|
||||
std::pair<bool, bool>
|
||||
MipsSEInstrInfo::compareOpndSize(unsigned Opc,
|
||||
const MachineFunction &MF) const {
|
||||
|
|
|
|||
|
|
@ -82,6 +82,8 @@ private:
|
|||
|
||||
void expandRetRA(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const;
|
||||
|
||||
void expandERet(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const;
|
||||
|
||||
std::pair<bool, bool> compareOpndSize(unsigned Opc,
|
||||
const MachineFunction &MF) const;
|
||||
|
||||
|
|
|
|||
|
|
@ -126,17 +126,19 @@ void MipsSERegisterInfo::eliminateFI(MachineBasicBlock::iterator II,
|
|||
}
|
||||
|
||||
bool EhDataRegFI = MipsFI->isEhDataRegFI(FrameIndex);
|
||||
|
||||
bool IsISRRegFI = MipsFI->isISRRegFI(FrameIndex);
|
||||
// The following stack frame objects are always referenced relative to $sp:
|
||||
// 1. Outgoing arguments.
|
||||
// 2. Pointer to dynamically allocated stack space.
|
||||
// 3. Locations for callee-saved registers.
|
||||
// 4. Locations for eh data registers.
|
||||
// 5. Locations for ISR saved Coprocessor 0 registers 12 & 14.
|
||||
// Everything else is referenced relative to whatever register
|
||||
// getFrameRegister() returns.
|
||||
unsigned FrameReg;
|
||||
|
||||
if ((FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI) || EhDataRegFI)
|
||||
if ((FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI) || EhDataRegFI ||
|
||||
IsISRRegFI)
|
||||
FrameReg = ABI.GetStackPtr();
|
||||
else if (RegInfo->needsStackRealignment(MF)) {
|
||||
if (MFI->hasVarSizedObjects() && !MFI->isFixedObjectIndex(FrameIndex))
|
||||
|
|
|
|||
|
|
@ -0,0 +1,11 @@
|
|||
; RUN: llc -mcpu=mips64r6 -march=mipsel -relocation-model=static -o - %s | FileCheck %s
|
||||
; XFAIL: *
|
||||
|
||||
define void @isr_sw0() #0 {
|
||||
call void bitcast (void (...)* @write to void ()*)()
|
||||
}
|
||||
|
||||
declare void @write(...)
|
||||
|
||||
attributes #0 = { "interrupt"="sw0" }
|
||||
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
; RUN: llc -mcpu=mips32r2 -march=mipsel -relocation-model=static -o - %s | FileCheck %s
|
||||
; XFAIL: *
|
||||
|
||||
define void @isr_sw0(i8 signext %n) #0 {
|
||||
call void bitcast (void (...)* @write to void ()*)()
|
||||
}
|
||||
|
||||
declare void @write(...)
|
||||
|
||||
attributes #0 = { "interrupt"="sw0" }
|
||||
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
; RUN: llc -mcpu=mips32 -march=mipsel -relocation-model=static -o - %s | FileCheck %s
|
||||
; XFAIL: *
|
||||
|
||||
define void @isr_sw0() #0 {
|
||||
call void bitcast (void (...)* @write to void ()*)()
|
||||
}
|
||||
|
||||
declare void @write(...)
|
||||
|
||||
attributes #0 = { "interrupt"="sw0" }
|
||||
|
||||
|
|
@ -0,0 +1,244 @@
|
|||
; RUN: llc -mcpu=mips32r2 -march=mipsel -relocation-model=static -o - %s | FileCheck %s
|
||||
|
||||
define void @isr_sw0() #0 {
|
||||
; CHECK-LABEL: isr_sw0:
|
||||
; CHECK: mfc0 $27, $14, 0
|
||||
; CHECK: sw $27, [[R1:[0-9]+]]($sp)
|
||||
; CHECK: mfc0 $27, $12, 0
|
||||
; CHECK: sw $27, [[R2:[0-9]+]]($sp)
|
||||
; CHECK: ins $27, $zero, 8, 1
|
||||
; CHECK: ins $27, $zero, 1, 4
|
||||
; CHECK: ins $27, $zero, 29, 1
|
||||
; CHECK: mtc0 $27, $12, 0
|
||||
; Must save all registers
|
||||
; CHECK: sw $7, {{[0-9]+}}($sp)
|
||||
; CHECK: sw $6, {{[0-9]+}}($sp)
|
||||
; CHECK: sw $5, {{[0-9]+}}($sp)
|
||||
; CHECK: sw $4, {{[0-9]+}}($sp)
|
||||
; CHECK: sw $3, {{[0-9]+}}($sp)
|
||||
; CHECK: sw $2, {{[0-9]+}}($sp)
|
||||
; CHECK: sw $25, {{[0-9]+}}($sp)
|
||||
; CHECK: sw $24, {{[0-9]+}}($sp)
|
||||
; CHECK: sw $15, {{[0-9]+}}($sp)
|
||||
; CHECK: sw $14, {{[0-9]+}}($sp)
|
||||
; CHECK: sw $13, {{[0-9]+}}($sp)
|
||||
; CHECK: sw $12, {{[0-9]+}}($sp)
|
||||
; CHECK: sw $11, {{[0-9]+}}($sp)
|
||||
; CHECK: sw $10, {{[0-9]+}}($sp)
|
||||
; CHECK: sw $9, {{[0-9]+}}($sp)
|
||||
; CHECK: sw $8, {{[0-9]+}}($sp)
|
||||
; CHECK: sw $ra, [[R5:[0-9]+]]($sp)
|
||||
; CHECK: sw $gp, {{[0-9]+}}($sp)
|
||||
; CHECK: sw $1, {{[0-9]+}}($sp)
|
||||
; CHECK: mflo $26
|
||||
; CHECK: sw $26, [[R3:[0-9]+]]($sp)
|
||||
; CHECK: mfhi $26
|
||||
; CHECK: sw $26, [[R4:[0-9]+]]($sp)
|
||||
call void bitcast (void (...)* @write to void ()*)()
|
||||
; CHECK: lw $26, [[R4:[0-9]+]]($sp)
|
||||
; CHECK: mthi $26
|
||||
; CHECK: lw $26, [[R3:[0-9]+]]($sp)
|
||||
; CHECK: mtlo $26
|
||||
; CHECK: lw $1, {{[0-9]+}}($sp)
|
||||
; CHECK: lw $gp, {{[0-9]+}}($sp)
|
||||
; CHECK: lw $ra, [[R5:[0-9]+]]($sp)
|
||||
; CHECK: lw $8, {{[0-9]+}}($sp)
|
||||
; CHECK: lw $9, {{[0-9]+}}($sp)
|
||||
; CHECK: lw $10, {{[0-9]+}}($sp)
|
||||
; CHECK: lw $11, {{[0-9]+}}($sp)
|
||||
; CHECK: lw $12, {{[0-9]+}}($sp)
|
||||
; CHECK: lw $13, {{[0-9]+}}($sp)
|
||||
; CHECK: lw $14, {{[0-9]+}}($sp)
|
||||
; CHECK: lw $15, {{[0-9]+}}($sp)
|
||||
; CHECK: lw $24, {{[0-9]+}}($sp)
|
||||
; CHECK: lw $25, {{[0-9]+}}($sp)
|
||||
; CHECK: lw $2, {{[0-9]+}}($sp)
|
||||
; CHECK: lw $3, {{[0-9]+}}($sp)
|
||||
; CHECK: lw $4, {{[0-9]+}}($sp)
|
||||
; CHECK: lw $5, {{[0-9]+}}($sp)
|
||||
; CHECK: lw $6, {{[0-9]+}}($sp)
|
||||
; CHECK: lw $7, {{[0-9]+}}($sp)
|
||||
; CHECK: di
|
||||
; CHECK: ehb
|
||||
; CHECK: lw $27, [[R2:[0-9]+]]($sp)
|
||||
; CHECK: mtc0 $27, $14, 0
|
||||
; CHECK: lw $27, [[R1:[0-9]+]]($sp)
|
||||
; CHECK: mtc0 $27, $12, 0
|
||||
; CHECK: eret
|
||||
ret void
|
||||
}
|
||||
|
||||
declare void @write(...)
|
||||
|
||||
define void @isr_sw1() #2 {
|
||||
; CHECK-LABEL: isr_sw1:
|
||||
; CHECK: mfc0 $27, $14, 0
|
||||
; CHECK: sw $27, {{[0-9]+}}($sp)
|
||||
; CHECK: mfc0 $27, $12, 0
|
||||
; CHECK: sw $27, {{[0-9]+}}($sp)
|
||||
; CHECK: ins $27, $zero, 8, 2
|
||||
; CHECK: ins $27, $zero, 1, 4
|
||||
; CHECK: ins $27, $zero, 29, 1
|
||||
; CHECK: mtc0 $27, $12, 0
|
||||
ret void
|
||||
; CHECK: di
|
||||
; CHECK: ehb
|
||||
; CHECK: lw $27, {{[0-9]+}}($sp)
|
||||
; CHECK: mtc0 $27, $14, 0
|
||||
; CHECK: lw $27, {{[0-9]+}}($sp)
|
||||
; CHECK: mtc0 $27, $12, 0
|
||||
; CHECK: eret
|
||||
}
|
||||
|
||||
define void @isr_hw0() #3 {
|
||||
; CHECK-LABEL: isr_hw0:
|
||||
; CHECK: mfc0 $27, $14, 0
|
||||
; CHECK: sw $27, {{[0-9]+}}($sp)
|
||||
; CHECK: mfc0 $27, $12, 0
|
||||
; CHECK: sw $27, {{[0-9]+}}($sp)
|
||||
; CHECK: ins $27, $zero, 8, 3
|
||||
; CHECK: ins $27, $zero, 1, 4
|
||||
; CHECK: ins $27, $zero, 29, 1
|
||||
; CHECK: mtc0 $27, $12, 0
|
||||
ret void
|
||||
; CHECK: di
|
||||
; CHECK: ehb
|
||||
; CHECK: lw $27, {{[0-9]+}}($sp)
|
||||
; CHECK: mtc0 $27, $14, 0
|
||||
; CHECK: lw $27, {{[0-9]+}}($sp)
|
||||
; CHECK: mtc0 $27, $12, 0
|
||||
; CHECK: eret
|
||||
}
|
||||
|
||||
define void @isr_hw1() #4 {
|
||||
; CHECK-LABEL: isr_hw1:
|
||||
; CHECK: mfc0 $27, $14, 0
|
||||
; CHECK: sw $27, {{[0-9]+}}($sp)
|
||||
; CHECK: mfc0 $27, $12, 0
|
||||
; CHECK: sw $27, {{[0-9]+}}($sp)
|
||||
; CHECK: ins $27, $zero, 8, 4
|
||||
; CHECK: ins $27, $zero, 1, 4
|
||||
; CHECK: ins $27, $zero, 29, 1
|
||||
; CHECK: mtc0 $27, $12, 0
|
||||
ret void
|
||||
; CHECK: di
|
||||
; CHECK: ehb
|
||||
; CHECK: lw $27, {{[0-9]+}}($sp)
|
||||
; CHECK: mtc0 $27, $14, 0
|
||||
; CHECK: lw $27, {{[0-9]+}}($sp)
|
||||
; CHECK: mtc0 $27, $12, 0
|
||||
; CHECK: eret
|
||||
}
|
||||
|
||||
|
||||
define void @isr_hw2() #5 {
|
||||
; CHECK-LABEL: isr_hw2:
|
||||
; CHECK: mfc0 $27, $14, 0
|
||||
; CHECK: sw $27, {{[0-9]+}}($sp)
|
||||
; CHECK: mfc0 $27, $12, 0
|
||||
; CHECK: sw $27, {{[0-9]+}}($sp)
|
||||
; CHECK: ins $27, $zero, 8, 5
|
||||
; CHECK: ins $27, $zero, 1, 4
|
||||
; CHECK: ins $27, $zero, 29, 1
|
||||
; CHECK: mtc0 $27, $12, 0
|
||||
ret void
|
||||
; CHECK: di
|
||||
; CHECK: ehb
|
||||
; CHECK: lw $27, {{[0-9]+}}($sp)
|
||||
; CHECK: mtc0 $27, $14, 0
|
||||
; CHECK: lw $27, {{[0-9]+}}($sp)
|
||||
; CHECK: mtc0 $27, $12, 0
|
||||
; CHECK: eret
|
||||
}
|
||||
|
||||
define void @isr_hw3() #6 {
|
||||
; CHECK-LABEL: isr_hw3:
|
||||
; CHECK: mfc0 $27, $14, 0
|
||||
; CHECK: sw $27, {{[0-9]+}}($sp)
|
||||
; CHECK: mfc0 $27, $12, 0
|
||||
; CHECK: sw $27, {{[0-9]+}}($sp)
|
||||
; CHECK: ins $27, $zero, 8, 6
|
||||
; CHECK: ins $27, $zero, 1, 4
|
||||
; CHECK: ins $27, $zero, 29, 1
|
||||
; CHECK: mtc0 $27, $12, 0
|
||||
ret void
|
||||
; CHECK: di
|
||||
; CHECK: ehb
|
||||
; CHECK: lw $27, {{[0-9]+}}($sp)
|
||||
; CHECK: mtc0 $27, $14, 0
|
||||
; CHECK: lw $27, {{[0-9]+}}($sp)
|
||||
; CHECK: mtc0 $27, $12, 0
|
||||
; CHECK: eret
|
||||
}
|
||||
|
||||
define void @isr_hw4() #7 {
|
||||
; CHECK-LABEL: isr_hw4:
|
||||
; CHECK: mfc0 $27, $14, 0
|
||||
; CHECK: sw $27, {{[0-9]+}}($sp)
|
||||
; CHECK: mfc0 $27, $12, 0
|
||||
; CHECK: sw $27, {{[0-9]+}}($sp)
|
||||
; CHECK: ins $27, $zero, 8, 7
|
||||
; CHECK: ins $27, $zero, 1, 4
|
||||
; CHECK: ins $27, $zero, 29, 1
|
||||
; CHECK: mtc0 $27, $12, 0
|
||||
ret void
|
||||
; CHECK: di
|
||||
; CHECK: ehb
|
||||
; CHECK: lw $27, {{[0-9]+}}($sp)
|
||||
; CHECK: mtc0 $27, $14, 0
|
||||
; CHECK: lw $27, {{[0-9]+}}($sp)
|
||||
; CHECK: mtc0 $27, $12, 0
|
||||
; CHECK: eret
|
||||
}
|
||||
|
||||
define void @isr_hw5() #8 {
|
||||
; CHECK-LABEL: isr_hw5:
|
||||
; CHECK: mfc0 $27, $14, 0
|
||||
; CHECK: sw $27, {{[0-9]+}}($sp)
|
||||
; CHECK: mfc0 $27, $12, 0
|
||||
; CHECK: sw $27, {{[0-9]+}}($sp)
|
||||
; CHECK: ins $27, $zero, 8, 8
|
||||
; CHECK: ins $27, $zero, 1, 4
|
||||
; CHECK: ins $27, $zero, 29, 1
|
||||
; CHECK: mtc0 $27, $12, 0
|
||||
ret void
|
||||
; CHECK: di
|
||||
; CHECK: ehb
|
||||
; CHECK: lw $27, {{[0-9]+}}($sp)
|
||||
; CHECK: mtc0 $27, $14, 0
|
||||
; CHECK: lw $27, {{[0-9]+}}($sp)
|
||||
; CHECK: mtc0 $27, $12, 0
|
||||
; CHECK: eret
|
||||
}
|
||||
|
||||
define void @isr_eic() #9 {
|
||||
; CHECK-LABEL: isr_eic:
|
||||
; CHECK: mfc0 $26, $13, 0
|
||||
; CHECK: ext $26, $26, 10, 6
|
||||
; CHECK: mfc0 $27, $14, 0
|
||||
; CHECK: sw $27, {{[0-9]+}}($sp)
|
||||
; CHECK: mfc0 $27, $12, 0
|
||||
; CHECK: sw $27, {{[0-9]+}}($sp)
|
||||
; CHECK: ins $27, $26, 10, 6
|
||||
; CHECK: ins $27, $zero, 1, 4
|
||||
; CHECK: ins $27, $zero, 29, 1
|
||||
; CHECK: mtc0 $27, $12, 0
|
||||
ret void
|
||||
; CHECK: di
|
||||
; CHECK: ehb
|
||||
; CHECK: lw $27, {{[0-9]+}}($sp)
|
||||
; CHECK: mtc0 $27, $14, 0
|
||||
; CHECK: lw $27, {{[0-9]+}}($sp)
|
||||
; CHECK: mtc0 $27, $12, 0
|
||||
; CHECK: eret
|
||||
}
|
||||
|
||||
attributes #0 = { "interrupt"="sw0" }
|
||||
attributes #2 = { "interrupt"="sw1" }
|
||||
attributes #3 = { "interrupt"="hw0" }
|
||||
attributes #4 = { "interrupt"="hw1" }
|
||||
attributes #5 = { "interrupt"="hw2" }
|
||||
attributes #6 = { "interrupt"="hw3" }
|
||||
attributes #7 = { "interrupt"="hw4" }
|
||||
attributes #8 = { "interrupt"="hw5" }
|
||||
attributes #9 = { "interrupt"="eic" }
|
||||
Loading…
Reference in New Issue