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Tidy up. 80 columns and argument alignment. 

llvm-svn: 155319
This commit is contained in:
Craig Topper 2012-04-22 18:51:37 +00:00
parent ad56a744f1
commit 43397c0900
1 changed files with 17 additions and 18 deletions
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21
llvm/lib/Target/X86/X86ISelLowering.cpp
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@ -13042,7 +13042,8 @@ SDValue X86TargetLowering::PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
Op = DAG.getVectorShuffle(MVT::v8i32, dl, Op, DAG.getUNDEF(MVT::v8i32),
ShufMask);
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Op, DAG.getIntPtrConstant(0));
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Op,
DAG.getIntPtrConstant(0));
}
// AVX: v4i64 -> v4i32
@ -13058,22 +13059,22 @@ SDValue X86TargetLowering::PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
// PSHUFD
static const int ShufMask1[] = {0, 2, 0, 0};
OpLo = DAG.getVectorShuffle(VT, dl, OpLo, DAG.getUNDEF(VT),
ShufMask1);
OpHi = DAG.getVectorShuffle(VT, dl, OpHi, DAG.getUNDEF(VT),
ShufMask1);
OpLo = DAG.getVectorShuffle(VT, dl, OpLo, DAG.getUNDEF(VT), ShufMask1);
OpHi = DAG.getVectorShuffle(VT, dl, OpHi, DAG.getUNDEF(VT), ShufMask1);
// MOVLHPS
static const int ShufMask2[] = {0, 1, 4, 5};
return DAG.getVectorShuffle(VT, dl, OpLo, OpHi, ShufMask2);
}
if ((VT == MVT::v8i16) && (OpVT == MVT::v8i32)) {
if (Subtarget->hasAVX2()) {
// AVX2: v8i32 -> v8i16
Op = DAG.getNode(ISD::BITCAST, dl, MVT::v32i8, Op);
// PSHUFB
SmallVector<SDValue,32> pshufbMask;
for (unsigned i = 0; i < 2; ++i) {
@ -13088,8 +13089,8 @@ SDValue X86TargetLowering::PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
for (unsigned j = 0; j < 8; ++j)
pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
}
SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v32i8, &pshufbMask[0],
32);
SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v32i8,
&pshufbMask[0], 32);
Op = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, Op, BV);
Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i64, Op);
@ -13117,11 +13118,9 @@ SDValue X86TargetLowering::PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
-1, -1, -1, -1, -1, -1, -1, -1};
OpLo = DAG.getVectorShuffle(MVT::v16i8, dl, OpLo,
DAG.getUNDEF(MVT::v16i8),
OpLo = DAG.getVectorShuffle(MVT::v16i8, dl, OpLo, DAG.getUNDEF(MVT::v16i8),
ShufMask1);
OpHi = DAG.getVectorShuffle(MVT::v16i8, dl, OpHi,
DAG.getUNDEF(MVT::v16i8),
OpHi = DAG.getVectorShuffle(MVT::v16i8, dl, OpHi, DAG.getUNDEF(MVT::v16i8),
ShufMask1);
OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);