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[AMDGPU] Added checks for dpp_ctrl value 

- Report error for invalid dpp_ctrl values.
- Changed the way it is reported, now the error will be emitted into
  asm and will work with release build as well.
- Added dpp_ctrl value verifier for codegen.
- Added symbolic constants for dpp_ctrl.

Differential Revision: https://reviews.llvm.org/D46565

llvm-svn: 331775
This commit is contained in:
Stanislav Mekhanoshin 2018-05-08 16:53:02 +00:00
parent 610e621c99
commit 432936161e
4 changed files with 99 additions and 36 deletions
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50
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
View File

@ -4710,21 +4710,23 @@ void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst,
//===----------------------------------------------------------------------===//
bool AMDGPUOperand::isDPPCtrl() const {
using namespace AMDGPU::DPP;
bool result = isImm() && getImmTy() == ImmTyDppCtrl && isUInt<9>(getImm());
if (result) {
int64_t Imm = getImm();
return ((Imm >= 0x000) && (Imm <= 0x0ff)) ||
((Imm >= 0x101) && (Imm <= 0x10f)) ||
((Imm >= 0x111) && (Imm <= 0x11f)) ||
((Imm >= 0x121) && (Imm <= 0x12f)) ||
(Imm == 0x130) ||
(Imm == 0x134) ||
(Imm == 0x138) ||
(Imm == 0x13c) ||
(Imm == 0x140) ||
(Imm == 0x141) ||
(Imm == 0x142) ||
(Imm == 0x143);
return (Imm >= DppCtrl::QUAD_PERM_FIRST && Imm <= DppCtrl::QUAD_PERM_LAST) ||
(Imm >= DppCtrl::ROW_SHL_FIRST && Imm <= DppCtrl::ROW_SHL_LAST) ||
(Imm >= DppCtrl::ROW_SHR_FIRST && Imm <= DppCtrl::ROW_SHR_LAST) ||
(Imm >= DppCtrl::ROW_ROR_FIRST && Imm <= DppCtrl::ROW_ROR_LAST) ||
(Imm == DppCtrl::WAVE_SHL1) ||
(Imm == DppCtrl::WAVE_ROL1) ||
(Imm == DppCtrl::WAVE_SHR1) ||
(Imm == DppCtrl::WAVE_ROR1) ||
(Imm == DppCtrl::ROW_MIRROR) ||
(Imm == DppCtrl::ROW_HALF_MIRROR) ||
(Imm == DppCtrl::BCAST15) ||
(Imm == DppCtrl::BCAST31);
}
return false;
}
@ -4743,6 +4745,8 @@ bool AMDGPUOperand::isU16Imm() const {
OperandMatchResultTy
AMDGPUAsmParser::parseDPPCtrl(OperandVector &Operands) {
using namespace AMDGPU::DPP;
SMLoc S = Parser.getTok().getLoc();
StringRef Prefix;
int64_t Int;
@ -4754,10 +4758,10 @@ AMDGPUAsmParser::parseDPPCtrl(OperandVector &Operands) {
}
if (Prefix == "row_mirror") {
Int = 0x140;
Int = DppCtrl::ROW_MIRROR;
Parser.Lex();
} else if (Prefix == "row_half_mirror") {
Int = 0x141;
Int = DppCtrl::ROW_HALF_MIRROR;
Parser.Lex();
} else {
// Check to prevent parseDPPCtrlOps from eating invalid tokens
@ -4809,24 +4813,24 @@ AMDGPUAsmParser::parseDPPCtrl(OperandVector &Operands) {
return MatchOperand_ParseFail;
if (Prefix == "row_shl" && 1 <= Int && Int <= 15) {
Int |= 0x100;
Int |= DppCtrl::ROW_SHL0;
} else if (Prefix == "row_shr" && 1 <= Int && Int <= 15) {
Int |= 0x110;
Int |= DppCtrl::ROW_SHR0;
} else if (Prefix == "row_ror" && 1 <= Int && Int <= 15) {
Int |= 0x120;
Int |= DppCtrl::ROW_ROR0;
} else if (Prefix == "wave_shl" && 1 == Int) {
Int = 0x130;
Int = DppCtrl::WAVE_SHL1;
} else if (Prefix == "wave_rol" && 1 == Int) {
Int = 0x134;
Int = DppCtrl::WAVE_ROL1;
} else if (Prefix == "wave_shr" && 1 == Int) {
Int = 0x138;
Int = DppCtrl::WAVE_SHR1;
} else if (Prefix == "wave_ror" && 1 == Int) {
Int = 0x13C;
Int = DppCtrl::WAVE_ROR1;
} else if (Prefix == "row_bcast") {
if (Int == 15) {
Int = 0x142;
Int = DppCtrl::BCAST15;
} else if (Int == 31) {
Int = 0x143;
Int = DppCtrl::BCAST31;
} else {
return MatchOperand_ParseFail;
}

31
llvm/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
View File

@ -631,40 +631,45 @@ void AMDGPUInstPrinter::printOperandAndIntInputMods(const MCInst *MI,
void AMDGPUInstPrinter::printDPPCtrl(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O) {
using namespace AMDGPU::DPP;
unsigned Imm = MI->getOperand(OpNo).getImm();
if (Imm <= 0x0ff) {
if (Imm <= DppCtrl::QUAD_PERM_LAST) {
O << " quad_perm:[";
O << formatDec(Imm & 0x3) << ',';
O << formatDec((Imm & 0xc) >> 2) << ',';
O << formatDec((Imm & 0x30) >> 4) << ',';
O << formatDec((Imm & 0xc0) >> 6) << ']';
} else if ((Imm >= 0x101) && (Imm <= 0x10f)) {
} else if ((Imm >= DppCtrl::ROW_SHL_FIRST) &&
(Imm <= DppCtrl::ROW_SHL_LAST)) {
O << " row_shl:";
printU4ImmDecOperand(MI, OpNo, O);
} else if ((Imm >= 0x111) && (Imm <= 0x11f)) {
} else if ((Imm >= DppCtrl::ROW_SHR_FIRST) &&
(Imm <= DppCtrl::ROW_SHR_LAST)) {
O << " row_shr:";
printU4ImmDecOperand(MI, OpNo, O);
} else if ((Imm >= 0x121) && (Imm <= 0x12f)) {
} else if ((Imm >= DppCtrl::ROW_ROR_FIRST) &&
(Imm <= DppCtrl::ROW_ROR_LAST)) {
O << " row_ror:";
printU4ImmDecOperand(MI, OpNo, O);
} else if (Imm == 0x130) {
} else if (Imm == DppCtrl::WAVE_SHL1) {
O << " wave_shl:1";
} else if (Imm == 0x134) {
} else if (Imm == DppCtrl::WAVE_ROL1) {
O << " wave_rol:1";
} else if (Imm == 0x138) {
} else if (Imm == DppCtrl::WAVE_SHR1) {
O << " wave_shr:1";
} else if (Imm == 0x13c) {
} else if (Imm == DppCtrl::WAVE_ROR1) {
O << " wave_ror:1";
} else if (Imm == 0x140) {
} else if (Imm == DppCtrl::ROW_MIRROR) {
O << " row_mirror";
} else if (Imm == 0x141) {
} else if (Imm == DppCtrl::ROW_HALF_MIRROR) {
O << " row_half_mirror";
} else if (Imm == 0x142) {
} else if (Imm == DppCtrl::BCAST15) {
O << " row_bcast:15";
} else if (Imm == 0x143) {
} else if (Imm == DppCtrl::BCAST31) {
O << " row_bcast:31";
} else {
llvm_unreachable("Invalid dpp_ctrl value");
O << " /* Invalid dpp_ctrl value */";
}
}

38
llvm/lib/Target/AMDGPU/SIDefines.h
View File

@ -385,6 +385,44 @@ enum SDWA9EncValues{
};
} // namespace SDWA
namespace DPP {
enum DppCtrl {
QUAD_PERM_FIRST = 0,
QUAD_PERM_LAST = 0xFF,
DPP_UNUSED1 = 0x100,
ROW_SHL0 = 0x100,
ROW_SHL_FIRST = 0x101,
ROW_SHL_LAST = 0x10F,
DPP_UNUSED2 = 0x110,
ROW_SHR0 = 0x110,
ROW_SHR_FIRST = 0x111,
ROW_SHR_LAST = 0x11F,
DPP_UNUSED3 = 0x120,
ROW_ROR0 = 0x120,
ROW_ROR_FIRST = 0x121,
ROW_ROR_LAST = 0x12F,
WAVE_SHL1 = 0x130,
DPP_UNUSED4_FIRST = 0x131,
DPP_UNUSED4_LAST = 0x133,
WAVE_ROL1 = 0x134,
DPP_UNUSED5_FIRST = 0x135,
DPP_UNUSED5_LAST = 0x137,
WAVE_SHR1 = 0x138,
DPP_UNUSED6_FIRST = 0x139,
DPP_UNUSED6_LAST = 0x13B,
WAVE_ROR1 = 0x13C,
DPP_UNUSED7_FIRST = 0x13D,
DPP_UNUSED7_LAST = 0x13F,
ROW_MIRROR = 0x140,
ROW_HALF_MIRROR = 0x141,
BCAST15 = 0x142,
BCAST31 = 0x143,
DPP_LAST = BCAST31
};
} // namespace DPP
} // namespace AMDGPU
#define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028

16
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
View File

@ -2869,6 +2869,22 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
}
}
const MachineOperand *DppCt = getNamedOperand(MI, AMDGPU::OpName::dpp_ctrl);
if (DppCt) {
using namespace AMDGPU::DPP;
unsigned DC = DppCt->getImm();
if (DC == DppCtrl::DPP_UNUSED1 || DC == DppCtrl::DPP_UNUSED2 ||
DC == DppCtrl::DPP_UNUSED3 || DC > DppCtrl::DPP_LAST ||
(DC >= DppCtrl::DPP_UNUSED4_FIRST && DC <= DppCtrl::DPP_UNUSED4_LAST) ||
(DC >= DppCtrl::DPP_UNUSED5_FIRST && DC <= DppCtrl::DPP_UNUSED5_LAST) ||
(DC >= DppCtrl::DPP_UNUSED6_FIRST && DC <= DppCtrl::DPP_UNUSED6_LAST) ||
(DC >= DppCtrl::DPP_UNUSED7_FIRST && DC <= DppCtrl::DPP_UNUSED7_LAST)) {
ErrInfo = "Invalid dpp_ctrl value";
return false;
}
}
return true;
}