[FastISel][AArch64] Fix "Fold sign-/zero-extends into the load instruction."
This commit fixes an issue with sign-/zero-extending loads that was discovered by Richard Barton. We use now the correct load instructions for sign-extending loads to 64bit. Also updated and added more unit tests. llvm-svn: 219185
This commit is contained in:
Juergen Ributzka
parent
cb69583c50
commit
42bf665f2b
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@ -178,8 +178,8 @@ private:
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bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt);
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bool emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm);
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bool emitFCmp(MVT RetVT, const Value *LHS, const Value *RHS);
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bool emitLoad(MVT VT, unsigned &ResultReg, Address Addr, bool WantZExt = true,
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MachineMemOperand *MMO = nullptr);
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bool emitLoad(MVT VT, MVT ResultVT, unsigned &ResultReg, Address Addr,
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bool WantZExt = true, MachineMemOperand *MMO = nullptr);
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bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
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MachineMemOperand *MMO = nullptr);
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unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
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@ -260,6 +260,8 @@ public:
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static bool isIntExtFree(const Instruction *I) {
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assert((isa<ZExtInst>(I) || isa<SExtInst>(I)) &&
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"Unexpected integer extend instruction.");
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assert(!I->getType()->isVectorTy() && I->getType()->isIntegerTy() &&
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"Unexpected value type.");
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bool IsZExt = isa<ZExtInst>(I);
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if (const auto *LI = dyn_cast<LoadInst>(I->getOperand(0)))
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@ -1589,8 +1591,9 @@ unsigned AArch64FastISel::emitAnd_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
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return emitLogicalOp_ri(ISD::AND, RetVT, LHSReg, LHSIsKill, Imm);
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}
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bool AArch64FastISel::emitLoad(MVT VT, unsigned &ResultReg, Address Addr,
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bool WantZExt, MachineMemOperand *MMO) {
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bool AArch64FastISel::emitLoad(MVT VT, MVT RetVT, unsigned &ResultReg,
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Address Addr, bool WantZExt,
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MachineMemOperand *MMO) {
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// Simplify this down to something we can handle.
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if (!simplifyAddress(Addr, VT))
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return false;
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@ -1607,24 +1610,40 @@ bool AArch64FastISel::emitLoad(MVT VT, unsigned &ResultReg, Address Addr,
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ScaleFactor = 1;
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}
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static const unsigned GPOpcTable[2][4][4] = {
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static const unsigned GPOpcTable[2][8][4] = {
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// Sign-extend.
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{ { AArch64::LDURSBWi, AArch64::LDURSHWi, AArch64::LDURSWi,
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{ { AArch64::LDURSBWi, AArch64::LDURSHWi, AArch64::LDURWi,
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AArch64::LDURXi },
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{ AArch64::LDRSBWui, AArch64::LDRSHWui, AArch64::LDRSWui,
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{ AArch64::LDURSBXi, AArch64::LDURSHXi, AArch64::LDURSWi,
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AArch64::LDURXi },
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{ AArch64::LDRSBWui, AArch64::LDRSHWui, AArch64::LDRWui,
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AArch64::LDRXui },
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{ AArch64::LDRSBWroX, AArch64::LDRSHWroX, AArch64::LDRSWroX,
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{ AArch64::LDRSBXui, AArch64::LDRSHXui, AArch64::LDRSWui,
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AArch64::LDRXui },
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{ AArch64::LDRSBWroX, AArch64::LDRSHWroX, AArch64::LDRWroX,
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AArch64::LDRXroX },
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{ AArch64::LDRSBWroW, AArch64::LDRSHWroW, AArch64::LDRSWroW,
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{ AArch64::LDRSBXroX, AArch64::LDRSHXroX, AArch64::LDRSWroX,
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AArch64::LDRXroX },
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{ AArch64::LDRSBWroW, AArch64::LDRSHWroW, AArch64::LDRWroW,
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AArch64::LDRXroW },
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{ AArch64::LDRSBXroW, AArch64::LDRSHXroW, AArch64::LDRSWroW,
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AArch64::LDRXroW }
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},
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// Zero-extend.
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{ { AArch64::LDURBBi, AArch64::LDURHHi, AArch64::LDURWi,
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AArch64::LDURXi },
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{ AArch64::LDURBBi, AArch64::LDURHHi, AArch64::LDURWi,
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AArch64::LDURXi },
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{ AArch64::LDRBBui, AArch64::LDRHHui, AArch64::LDRWui,
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AArch64::LDRXui },
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{ AArch64::LDRBBui, AArch64::LDRHHui, AArch64::LDRWui,
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AArch64::LDRXui },
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{ AArch64::LDRBBroX, AArch64::LDRHHroX, AArch64::LDRWroX,
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AArch64::LDRXroX },
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{ AArch64::LDRBBroX, AArch64::LDRHHroX, AArch64::LDRWroX,
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AArch64::LDRXroX },
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{ AArch64::LDRBBroW, AArch64::LDRHHroW, AArch64::LDRWroW,
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AArch64::LDRXroW },
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{ AArch64::LDRBBroW, AArch64::LDRHHroW, AArch64::LDRWroW,
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AArch64::LDRXroW }
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}
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@ -1646,24 +1665,28 @@ bool AArch64FastISel::emitLoad(MVT VT, unsigned &ResultReg, Address Addr,
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Addr.getExtendType() == AArch64_AM::SXTW)
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Idx++;
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bool IsRet64Bit = RetVT == MVT::i64;
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switch (VT.SimpleTy) {
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default:
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llvm_unreachable("Unexpected value type.");
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case MVT::i1: // Intentional fall-through.
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case MVT::i8:
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Opc = GPOpcTable[WantZExt][Idx][0];
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RC = &AArch64::GPR32RegClass;
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Opc = GPOpcTable[WantZExt][2 * Idx + IsRet64Bit][0];
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RC = (IsRet64Bit && !WantZExt) ?
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&AArch64::GPR64RegClass: &AArch64::GPR32RegClass;
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break;
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case MVT::i16:
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Opc = GPOpcTable[WantZExt][Idx][1];
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RC = &AArch64::GPR32RegClass;
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Opc = GPOpcTable[WantZExt][2 * Idx + IsRet64Bit][1];
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RC = (IsRet64Bit && !WantZExt) ?
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&AArch64::GPR64RegClass: &AArch64::GPR32RegClass;
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break;
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case MVT::i32:
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Opc = GPOpcTable[WantZExt][Idx][2];
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RC = WantZExt ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass;
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Opc = GPOpcTable[WantZExt][2 * Idx + IsRet64Bit][2];
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RC = (IsRet64Bit && !WantZExt) ?
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&AArch64::GPR64RegClass: &AArch64::GPR32RegClass;
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break;
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case MVT::i64:
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Opc = GPOpcTable[WantZExt][Idx][3];
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Opc = GPOpcTable[WantZExt][2 * Idx + IsRet64Bit][3];
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RC = &AArch64::GPR64RegClass;
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break;
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case MVT::f32:
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@ -1682,15 +1705,22 @@ bool AArch64FastISel::emitLoad(MVT VT, unsigned &ResultReg, Address Addr,
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TII.get(Opc), ResultReg);
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addLoadStoreOperands(Addr, MIB, MachineMemOperand::MOLoad, ScaleFactor, MMO);
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// For 32bit loads we do sign-extending loads to 64bit and then extract the
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// subreg. In the end this is just a NOOP.
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if (VT == MVT::i32 && !WantZExt)
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ResultReg = fastEmitInst_extractsubreg(MVT::i32, ResultReg, /*IsKill=*/true,
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AArch64::sub_32);
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// For zero-extending loads to 64bit we emit a 32bit load and then convert
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// the w-reg to an x-reg. In the end this is just an noop and will be removed.
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if (WantZExt && RetVT == MVT::i64 && VT <= MVT::i32) {
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unsigned Reg64 = createResultReg(&AArch64::GPR64RegClass);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(AArch64::SUBREG_TO_REG), Reg64)
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.addImm(0)
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.addReg(ResultReg, getKillRegState(true))
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.addImm(AArch64::sub_32);
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ResultReg = Reg64;
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}
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// Loading an i1 requires special handling.
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if (VT == MVT::i1) {
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unsigned ANDReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, 1);
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unsigned ANDReg = emitAnd_ri(IsRet64Bit ? MVT::i64 : MVT::i32, ResultReg,
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/*IsKill=*/true, 1);
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assert(ANDReg && "Unexpected AND instruction emission failure.");
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ResultReg = ANDReg;
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}
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@ -1767,11 +1797,21 @@ bool AArch64FastISel::selectLoad(const Instruction *I) {
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return false;
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bool WantZExt = true;
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if (I->hasOneUse() && isa<SExtInst>(I->use_begin()->getUser()))
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WantZExt = false;
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MVT RetVT = VT;
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if (I->hasOneUse()) {
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if (const auto *ZE = dyn_cast<ZExtInst>(I->use_begin()->getUser())) {
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if (!isTypeSupported(ZE->getType(), RetVT, /*IsVectorAllowed=*/false))
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RetVT = VT;
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} else if (const auto *SE = dyn_cast<SExtInst>(I->use_begin()->getUser())) {
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if (!isTypeSupported(SE->getType(), RetVT, /*IsVectorAllowed=*/false))
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RetVT = VT;
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WantZExt = false;
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}
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}
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unsigned ResultReg;
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if (!emitLoad(VT, ResultReg, Addr, WantZExt, createMachineMemOperandFor(I)))
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if (!emitLoad(VT, RetVT, ResultReg, Addr, WantZExt,
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createMachineMemOperandFor(I)))
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return false;
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updateValueMap(I, ResultReg);
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@ -2897,7 +2937,7 @@ bool AArch64FastISel::tryEmitSmallMemCpy(Address Dest, Address Src,
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bool RV;
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unsigned ResultReg;
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RV = emitLoad(VT, ResultReg, Src);
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RV = emitLoad(VT, VT, ResultReg, Src);
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if (!RV)
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return false;
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@ -3917,51 +3957,37 @@ bool AArch64FastISel::selectIntExt(const Instruction *I) {
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if (!isTypeSupported(I->getOperand(0)->getType(), SrcVT))
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return false;
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if (isIntExtFree(I)) {
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unsigned SrcReg = getRegForValue(I->getOperand(0));
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if (!SrcReg)
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return false;
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bool SrcIsKill = hasTrivialKill(I->getOperand(0));
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const TargetRegisterClass *RC = (RetVT == MVT::i64) ?
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&AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
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unsigned ResultReg = createResultReg(RC);
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if (RetVT == MVT::i64 && SrcVT != MVT::i64) {
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(AArch64::SUBREG_TO_REG), ResultReg)
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.addImm(0)
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.addReg(SrcReg, getKillRegState(SrcIsKill))
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.addImm(AArch64::sub_32);
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} else {
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(TargetOpcode::COPY), ResultReg)
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.addReg(SrcReg, getKillRegState(SrcIsKill));
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}
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updateValueMap(I, ResultReg);
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return true;
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}
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unsigned SrcReg = getRegForValue(I->getOperand(0));
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if (!SrcReg)
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return false;
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bool SrcRegIsKill = hasTrivialKill(I->getOperand(0));
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bool SrcIsKill = hasTrivialKill(I->getOperand(0));
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unsigned ResultReg = 0;
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if (isIntExtFree(I)) {
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if (RetVT == MVT::i64) {
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ResultReg = createResultReg(&AArch64::GPR64RegClass);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(AArch64::SUBREG_TO_REG), ResultReg)
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.addImm(0)
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.addReg(SrcReg, getKillRegState(SrcRegIsKill))
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.addImm(AArch64::sub_32);
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} else
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ResultReg = SrcReg;
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// The load instruction selection code handles the sign-/zero-extension.
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if (const auto *LI = dyn_cast<LoadInst>(I->getOperand(0))) {
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if (LI->hasOneUse()) {
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updateValueMap(I, SrcReg);
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return true;
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}
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}
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if (!ResultReg)
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ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, isa<ZExtInst>(I));
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bool IsZExt = isa<ZExtInst>(I);
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if (const auto *Arg = dyn_cast<Argument>(I->getOperand(0))) {
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if ((IsZExt && Arg->hasZExtAttr()) || (!IsZExt && Arg->hasSExtAttr())) {
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if (RetVT == MVT::i64 && SrcVT != MVT::i64) {
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unsigned ResultReg = createResultReg(&AArch64::GPR64RegClass);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(AArch64::SUBREG_TO_REG), ResultReg)
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.addImm(0)
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.addReg(SrcReg, getKillRegState(SrcIsKill))
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.addImm(AArch64::sub_32);
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SrcReg = ResultReg;
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}
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updateValueMap(I, SrcReg);
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return true;
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}
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}
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unsigned ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, IsZExt);
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if (!ResultReg)
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return false;
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@ -6,9 +6,9 @@
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;
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; SHIFT
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;
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define i64 @load_addr_shift_zext1(i32 zeroext %a, i64 %b) {
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define i64 @load_addr_shift_zext1(i32 %a, i64 %b) {
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; CHECK-LABEL: load_addr_shift_zext1
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; CHECK: ldr {{x[0-9]+}}, [x1, x0, lsl #3]
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; CHECK: ldr {{x[0-9]+}}, [x1, w0, uxtw #3]
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%1 = zext i32 %a to i64
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%2 = shl i64 %1, 3
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%3 = add i64 %b, %2
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@ -17,9 +17,9 @@ define i64 @load_addr_shift_zext1(i32 zeroext %a, i64 %b) {
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ret i64 %5
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}
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define i64 @load_addr_shift_zext2(i32 signext %a, i64 %b) {
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define i64 @load_addr_shift_zext2(i32 zeroext %a, i64 %b) {
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; CHECK-LABEL: load_addr_shift_zext2
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; CHECK: ldr {{x[0-9]+}}, [x1, w0, uxtw #3{{\]}}
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; CHECK: ldr {{x[0-9]+}}, [x1, x0, lsl #3]
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%1 = zext i32 %a to i64
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%2 = shl i64 %1, 3
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%3 = add i64 %b, %2
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@ -28,9 +28,20 @@ define i64 @load_addr_shift_zext2(i32 signext %a, i64 %b) {
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ret i64 %5
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}
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define i64 @load_addr_shift_sext1(i32 signext %a, i64 %b) {
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define i64 @load_addr_shift_zext3(i32 signext %a, i64 %b) {
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; CHECK-LABEL: load_addr_shift_zext3
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; CHECK: ldr {{x[0-9]+}}, [x1, w0, uxtw #3]
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%1 = zext i32 %a to i64
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%2 = shl i64 %1, 3
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%3 = add i64 %b, %2
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%4 = inttoptr i64 %3 to i64*
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%5 = load i64* %4
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ret i64 %5
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}
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define i64 @load_addr_shift_sext1(i32 %a, i64 %b) {
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; CHECK-LABEL: load_addr_shift_sext1
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; CHECK: ldr {{x[0-9]+}}, [x1, x0, lsl #3]
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; CHECK: ldr {{x[0-9]+}}, [x1, w0, sxtw #3]
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%1 = sext i32 %a to i64
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%2 = shl i64 %1, 3
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%3 = add i64 %b, %2
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@ -50,22 +61,22 @@ define i64 @load_addr_shift_sext2(i32 zeroext %a, i64 %b) {
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ret i64 %5
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}
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;
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; MUL
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;
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define i64 @load_addr_mul_zext1(i32 zeroext %a, i64 %b) {
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; CHECK-LABEL: load_addr_mul_zext1
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define i64 @load_addr_shift_sext3(i32 signext %a, i64 %b) {
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; CHECK-LABEL: load_addr_shift_sext3
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; CHECK: ldr {{x[0-9]+}}, [x1, x0, lsl #3]
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%1 = zext i32 %a to i64
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%2 = mul i64 %1, 8
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%1 = sext i32 %a to i64
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%2 = shl i64 %1, 3
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%3 = add i64 %b, %2
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%4 = inttoptr i64 %3 to i64*
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%5 = load i64* %4
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ret i64 %5
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}
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define i64 @load_addr_mul_zext2(i32 signext %a, i64 %b) {
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; CHECK-LABEL: load_addr_mul_zext2
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;
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; MUL
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;
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define i64 @load_addr_mul_zext1(i32 %a, i64 %b) {
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; CHECK-LABEL: load_addr_mul_zext1
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; CHECK: ldr {{x[0-9]+}}, [x1, w0, uxtw #3]
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%1 = zext i32 %a to i64
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%2 = mul i64 %1, 8
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@ -75,9 +86,31 @@ define i64 @load_addr_mul_zext2(i32 signext %a, i64 %b) {
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ret i64 %5
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}
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define i64 @load_addr_mul_sext1(i32 signext %a, i64 %b) {
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; CHECK-LABEL: load_addr_mul_sext1
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define i64 @load_addr_mul_zext2(i32 zeroext %a, i64 %b) {
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; CHECK-LABEL: load_addr_mul_zext2
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; CHECK: ldr {{x[0-9]+}}, [x1, x0, lsl #3]
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%1 = zext i32 %a to i64
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%2 = mul i64 %1, 8
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%3 = add i64 %b, %2
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%4 = inttoptr i64 %3 to i64*
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%5 = load i64* %4
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ret i64 %5
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}
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define i64 @load_addr_mul_zext3(i32 signext %a, i64 %b) {
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; CHECK-LABEL: load_addr_mul_zext3
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; CHECK: ldr {{x[0-9]+}}, [x1, w0, uxtw #3]
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||||
%1 = zext i32 %a to i64
|
||||
%2 = mul i64 %1, 8
|
||||
%3 = add i64 %b, %2
|
||||
%4 = inttoptr i64 %3 to i64*
|
||||
%5 = load i64* %4
|
||||
ret i64 %5
|
||||
}
|
||||
|
||||
define i64 @load_addr_mul_sext1(i32 %a, i64 %b) {
|
||||
; CHECK-LABEL: load_addr_mul_sext1
|
||||
; CHECK: ldr {{x[0-9]+}}, [x1, w0, sxtw #3]
|
||||
%1 = sext i32 %a to i64
|
||||
%2 = mul i64 %1, 8
|
||||
%3 = add i64 %b, %2
|
||||
|
|
@ -97,94 +130,372 @@ define i64 @load_addr_mul_sext2(i32 zeroext %a, i64 %b) {
|
|||
ret i64 %5
|
||||
}
|
||||
|
||||
define i64 @load_addr_mul_sext3(i32 signext %a, i64 %b) {
|
||||
; CHECK-LABEL: load_addr_mul_sext3
|
||||
; CHECK: ldr {{x[0-9]+}}, [x1, x0, lsl #3]
|
||||
%1 = sext i32 %a to i64
|
||||
%2 = mul i64 %1, 8
|
||||
%3 = add i64 %b, %2
|
||||
%4 = inttoptr i64 %3 to i64*
|
||||
%5 = load i64* %4
|
||||
ret i64 %5
|
||||
}
|
||||
|
||||
|
||||
;
|
||||
; Test folding of the sign-/zero-extend into the load instruction.
|
||||
define i32 @load_zext_i8_to_i32(i8* %a) {
|
||||
; CHECK-LABEL: load_zext_i8_to_i32
|
||||
; CHECK: ldrb w0, [x0]
|
||||
;
|
||||
|
||||
; Unscaled
|
||||
define i32 @load_unscaled_zext_i8_to_i32(i64 %a) {
|
||||
; CHECK-LABEL: load_unscaled_zext_i8_to_i32
|
||||
; CHECK: ldurb w0, [x0, #-8]
|
||||
; CHECK-NOT: uxtb
|
||||
%1 = load i8* %a
|
||||
%2 = zext i8 %1 to i32
|
||||
ret i32 %2
|
||||
%1 = add i64 %a, -8
|
||||
%2 = inttoptr i64 %1 to i8*
|
||||
%3 = load i8* %2
|
||||
%4 = zext i8 %3 to i32
|
||||
ret i32 %4
|
||||
}
|
||||
|
||||
define i32 @load_zext_i16_to_i32(i16* %a) {
|
||||
; CHECK-LABEL: load_zext_i16_to_i32
|
||||
; CHECK: ldrh w0, [x0]
|
||||
define i32 @load_unscaled_zext_i16_to_i32(i64 %a) {
|
||||
; CHECK-LABEL: load_unscaled_zext_i16_to_i32
|
||||
; CHECK: ldurh w0, [x0, #-8]
|
||||
; CHECK-NOT: uxth
|
||||
%1 = load i16* %a
|
||||
%2 = zext i16 %1 to i32
|
||||
ret i32 %2
|
||||
%1 = add i64 %a, -8
|
||||
%2 = inttoptr i64 %1 to i16*
|
||||
%3 = load i16* %2
|
||||
%4 = zext i16 %3 to i32
|
||||
ret i32 %4
|
||||
}
|
||||
|
||||
define i64 @load_zext_i8_to_i64(i8* %a) {
|
||||
; CHECK-LABEL: load_zext_i8_to_i64
|
||||
; CHECK: ldrb w0, [x0]
|
||||
define i64 @load_unscaled_zext_i8_to_i64(i64 %a) {
|
||||
; CHECK-LABEL: load_unscaled_zext_i8_to_i64
|
||||
; CHECK: ldurb w0, [x0, #-8]
|
||||
; CHECK-NOT: uxtb
|
||||
%1 = load i8* %a
|
||||
%2 = zext i8 %1 to i64
|
||||
ret i64 %2
|
||||
%1 = add i64 %a, -8
|
||||
%2 = inttoptr i64 %1 to i8*
|
||||
%3 = load i8* %2
|
||||
%4 = zext i8 %3 to i64
|
||||
ret i64 %4
|
||||
}
|
||||
|
||||
define i64 @load_zext_i16_to_i64(i16* %a) {
|
||||
; CHECK-LABEL: load_zext_i16_to_i64
|
||||
; CHECK: ldrh w0, [x0]
|
||||
define i64 @load_unscaled_zext_i16_to_i64(i64 %a) {
|
||||
; CHECK-LABEL: load_unscaled_zext_i16_to_i64
|
||||
; CHECK: ldurh w0, [x0, #-8]
|
||||
; CHECK-NOT: uxth
|
||||
%1 = load i16* %a
|
||||
%2 = zext i16 %1 to i64
|
||||
ret i64 %2
|
||||
%1 = add i64 %a, -8
|
||||
%2 = inttoptr i64 %1 to i16*
|
||||
%3 = load i16* %2
|
||||
%4 = zext i16 %3 to i64
|
||||
ret i64 %4
|
||||
}
|
||||
|
||||
define i64 @load_zext_i32_to_i64(i32* %a) {
|
||||
; CHECK-LABEL: load_zext_i32_to_i64
|
||||
; CHECK: ldr w0, [x0]
|
||||
define i64 @load_unscaled_zext_i32_to_i64(i64 %a) {
|
||||
; CHECK-LABEL: load_unscaled_zext_i32_to_i64
|
||||
; CHECK: ldur w0, [x0, #-8]
|
||||
; CHECK-NOT: uxtw
|
||||
%1 = load i32* %a
|
||||
%2 = zext i32 %1 to i64
|
||||
ret i64 %2
|
||||
%1 = add i64 %a, -8
|
||||
%2 = inttoptr i64 %1 to i32*
|
||||
%3 = load i32* %2
|
||||
%4 = zext i32 %3 to i64
|
||||
ret i64 %4
|
||||
}
|
||||
|
||||
define i32 @load_sext_i8_to_i32(i8* %a) {
|
||||
; CHECK-LABEL: load_sext_i8_to_i32
|
||||
; CHECK: ldrsb w0, [x0]
|
||||
define i32 @load_unscaled_sext_i8_to_i32(i64 %a) {
|
||||
; CHECK-LABEL: load_unscaled_sext_i8_to_i32
|
||||
; CHECK: ldursb w0, [x0, #-8]
|
||||
; CHECK-NOT: sxtb
|
||||
%1 = load i8* %a
|
||||
%2 = sext i8 %1 to i32
|
||||
ret i32 %2
|
||||
%1 = add i64 %a, -8
|
||||
%2 = inttoptr i64 %1 to i8*
|
||||
%3 = load i8* %2
|
||||
%4 = sext i8 %3 to i32
|
||||
ret i32 %4
|
||||
}
|
||||
|
||||
define i32 @load_sext_i16_to_i32(i16* %a) {
|
||||
; CHECK-LABEL: load_sext_i16_to_i32
|
||||
; CHECK: ldrsh w0, [x0]
|
||||
define i32 @load_unscaled_sext_i16_to_i32(i64 %a) {
|
||||
; CHECK-LABEL: load_unscaled_sext_i16_to_i32
|
||||
; CHECK: ldursh w0, [x0, #-8]
|
||||
; CHECK-NOT: sxth
|
||||
%1 = load i16* %a
|
||||
%2 = sext i16 %1 to i32
|
||||
ret i32 %2
|
||||
%1 = add i64 %a, -8
|
||||
%2 = inttoptr i64 %1 to i16*
|
||||
%3 = load i16* %2
|
||||
%4 = sext i16 %3 to i32
|
||||
ret i32 %4
|
||||
}
|
||||
|
||||
define i64 @load_sext_i8_to_i64(i8* %a) {
|
||||
; CHECK-LABEL: load_sext_i8_to_i64
|
||||
; CHECK: ldrsb w0, [x0]
|
||||
define i64 @load_unscaled_sext_i8_to_i64(i64 %a) {
|
||||
; CHECK-LABEL: load_unscaled_sext_i8_to_i64
|
||||
; CHECK: ldursb x0, [x0, #-8]
|
||||
; CHECK-NOT: sxtb
|
||||
%1 = load i8* %a
|
||||
%2 = sext i8 %1 to i64
|
||||
ret i64 %2
|
||||
%1 = add i64 %a, -8
|
||||
%2 = inttoptr i64 %1 to i8*
|
||||
%3 = load i8* %2
|
||||
%4 = sext i8 %3 to i64
|
||||
ret i64 %4
|
||||
}
|
||||
|
||||
define i64 @load_sext_i16_to_i64(i16* %a) {
|
||||
; CHECK-LABEL: load_sext_i16_to_i64
|
||||
; CHECK: ldrsh w0, [x0]
|
||||
define i64 @load_unscaled_sext_i16_to_i64(i64 %a) {
|
||||
; CHECK-LABEL: load_unscaled_sext_i16_to_i64
|
||||
; CHECK: ldursh x0, [x0, #-8]
|
||||
; CHECK-NOT: sxth
|
||||
%1 = load i16* %a
|
||||
%2 = sext i16 %1 to i64
|
||||
ret i64 %2
|
||||
%1 = add i64 %a, -8
|
||||
%2 = inttoptr i64 %1 to i16*
|
||||
%3 = load i16* %2
|
||||
%4 = sext i16 %3 to i64
|
||||
ret i64 %4
|
||||
}
|
||||
|
||||
define i64 @load_sext_i32_to_i64(i32* %a) {
|
||||
; CHECK-LABEL: load_sext_i32_to_i64
|
||||
; CHECK: ldrsw x0, [x0]
|
||||
define i64 @load_unscaled_sext_i32_to_i64(i64 %a) {
|
||||
; CHECK-LABEL: load_unscaled_sext_i32_to_i64
|
||||
; CHECK: ldursw x0, [x0, #-8]
|
||||
; CHECK-NOT: sxtw
|
||||
%1 = load i32* %a
|
||||
%2 = sext i32 %1 to i64
|
||||
ret i64 %2
|
||||
%1 = add i64 %a, -8
|
||||
%2 = inttoptr i64 %1 to i32*
|
||||
%3 = load i32* %2
|
||||
%4 = sext i32 %3 to i64
|
||||
ret i64 %4
|
||||
}
|
||||
|
||||
; Register
|
||||
define i32 @load_register_zext_i8_to_i32(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: load_register_zext_i8_to_i32
|
||||
; CHECK: ldrb w0, [x0, x1]
|
||||
; CHECK-NOT: uxtb
|
||||
%1 = add i64 %a, %b
|
||||
%2 = inttoptr i64 %1 to i8*
|
||||
%3 = load i8* %2
|
||||
%4 = zext i8 %3 to i32
|
||||
ret i32 %4
|
||||
}
|
||||
|
||||
define i32 @load_register_zext_i16_to_i32(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: load_register_zext_i16_to_i32
|
||||
; CHECK: ldrh w0, [x0, x1]
|
||||
; CHECK-NOT: uxth
|
||||
%1 = add i64 %a, %b
|
||||
%2 = inttoptr i64 %1 to i16*
|
||||
%3 = load i16* %2
|
||||
%4 = zext i16 %3 to i32
|
||||
ret i32 %4
|
||||
}
|
||||
|
||||
define i64 @load_register_zext_i8_to_i64(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: load_register_zext_i8_to_i64
|
||||
; CHECK: ldrb w0, [x0, x1]
|
||||
; CHECK-NOT: uxtb
|
||||
%1 = add i64 %a, %b
|
||||
%2 = inttoptr i64 %1 to i8*
|
||||
%3 = load i8* %2
|
||||
%4 = zext i8 %3 to i64
|
||||
ret i64 %4
|
||||
}
|
||||
|
||||
define i64 @load_register_zext_i16_to_i64(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: load_register_zext_i16_to_i64
|
||||
; CHECK: ldrh w0, [x0, x1]
|
||||
; CHECK-NOT: uxth
|
||||
%1 = add i64 %a, %b
|
||||
%2 = inttoptr i64 %1 to i16*
|
||||
%3 = load i16* %2
|
||||
%4 = zext i16 %3 to i64
|
||||
ret i64 %4
|
||||
}
|
||||
|
||||
define i64 @load_register_zext_i32_to_i64(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: load_register_zext_i32_to_i64
|
||||
; CHECK: ldr w0, [x0, x1]
|
||||
; CHECK-NOT: uxtw
|
||||
%1 = add i64 %a, %b
|
||||
%2 = inttoptr i64 %1 to i32*
|
||||
%3 = load i32* %2
|
||||
%4 = zext i32 %3 to i64
|
||||
ret i64 %4
|
||||
}
|
||||
|
||||
define i32 @load_register_sext_i8_to_i32(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: load_register_sext_i8_to_i32
|
||||
; CHECK: ldrsb w0, [x0, x1]
|
||||
; CHECK-NOT: sxtb
|
||||
%1 = add i64 %a, %b
|
||||
%2 = inttoptr i64 %1 to i8*
|
||||
%3 = load i8* %2
|
||||
%4 = sext i8 %3 to i32
|
||||
ret i32 %4
|
||||
}
|
||||
|
||||
define i32 @load_register_sext_i16_to_i32(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: load_register_sext_i16_to_i32
|
||||
; CHECK: ldrsh w0, [x0, x1]
|
||||
; CHECK-NOT: sxth
|
||||
%1 = add i64 %a, %b
|
||||
%2 = inttoptr i64 %1 to i16*
|
||||
%3 = load i16* %2
|
||||
%4 = sext i16 %3 to i32
|
||||
ret i32 %4
|
||||
}
|
||||
|
||||
define i64 @load_register_sext_i8_to_i64(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: load_register_sext_i8_to_i64
|
||||
; CHECK: ldrsb x0, [x0, x1]
|
||||
; CHECK-NOT: sxtb
|
||||
%1 = add i64 %a, %b
|
||||
%2 = inttoptr i64 %1 to i8*
|
||||
%3 = load i8* %2
|
||||
%4 = sext i8 %3 to i64
|
||||
ret i64 %4
|
||||
}
|
||||
|
||||
define i64 @load_register_sext_i16_to_i64(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: load_register_sext_i16_to_i64
|
||||
; CHECK: ldrsh x0, [x0, x1]
|
||||
; CHECK-NOT: sxth
|
||||
%1 = add i64 %a, %b
|
||||
%2 = inttoptr i64 %1 to i16*
|
||||
%3 = load i16* %2
|
||||
%4 = sext i16 %3 to i64
|
||||
ret i64 %4
|
||||
}
|
||||
|
||||
define i64 @load_register_sext_i32_to_i64(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: load_register_sext_i32_to_i64
|
||||
; CHECK: ldrsw x0, [x0, x1]
|
||||
; CHECK-NOT: sxtw
|
||||
%1 = add i64 %a, %b
|
||||
%2 = inttoptr i64 %1 to i32*
|
||||
%3 = load i32* %2
|
||||
%4 = sext i32 %3 to i64
|
||||
ret i64 %4
|
||||
}
|
||||
|
||||
; Extend
|
||||
define i32 @load_extend_zext_i8_to_i32(i64 %a, i32 %b) {
|
||||
; CHECK-LABEL: load_extend_zext_i8_to_i32
|
||||
; CHECK: sxtw [[REG:x[0-9]+]], w1
|
||||
; CHECK-NEXT: ldrb w0, [x0, [[REG]]]
|
||||
; CHECK-NOT: uxtb
|
||||
%1 = sext i32 %b to i64
|
||||
%2 = add i64 %a, %1
|
||||
%3 = inttoptr i64 %2 to i8*
|
||||
%4 = load i8* %3
|
||||
%5 = zext i8 %4 to i32
|
||||
ret i32 %5
|
||||
}
|
||||
|
||||
define i32 @load_extend_zext_i16_to_i32(i64 %a, i32 %b) {
|
||||
; CHECK-LABEL: load_extend_zext_i16_to_i32
|
||||
; CHECK: sxtw [[REG:x[0-9]+]], w1
|
||||
; CHECK-NEXT: ldrh w0, [x0, [[REG]]]
|
||||
; CHECK-NOT: uxth
|
||||
%1 = sext i32 %b to i64
|
||||
%2 = add i64 %a, %1
|
||||
%3 = inttoptr i64 %2 to i16*
|
||||
%4 = load i16* %3
|
||||
%5 = zext i16 %4 to i32
|
||||
ret i32 %5
|
||||
}
|
||||
|
||||
define i64 @load_extend_zext_i8_to_i64(i64 %a, i32 %b) {
|
||||
; CHECK-LABEL: load_extend_zext_i8_to_i64
|
||||
; CHECK: sxtw [[REG:x[0-9]+]], w1
|
||||
; CHECK-NEXT: ldrb w0, [x0, [[REG]]]
|
||||
; CHECK-NOT: uxtb
|
||||
%1 = sext i32 %b to i64
|
||||
%2 = add i64 %a, %1
|
||||
%3 = inttoptr i64 %2 to i8*
|
||||
%4 = load i8* %3
|
||||
%5 = zext i8 %4 to i64
|
||||
ret i64 %5
|
||||
}
|
||||
|
||||
define i64 @load_extend_zext_i16_to_i64(i64 %a, i32 %b) {
|
||||
; CHECK-LABEL: load_extend_zext_i16_to_i64
|
||||
; CHECK: sxtw [[REG:x[0-9]+]], w1
|
||||
; CHECK-NEXT: ldrh w0, [x0, [[REG]]]
|
||||
; CHECK-NOT: uxth
|
||||
%1 = sext i32 %b to i64
|
||||
%2 = add i64 %a, %1
|
||||
%3 = inttoptr i64 %2 to i16*
|
||||
%4 = load i16* %3
|
||||
%5 = zext i16 %4 to i64
|
||||
ret i64 %5
|
||||
}
|
||||
|
||||
define i64 @load_extend_zext_i32_to_i64(i64 %a, i32 %b) {
|
||||
; CHECK-LABEL: load_extend_zext_i32_to_i64
|
||||
; CHECK: sxtw [[REG:x[0-9]+]], w1
|
||||
; CHECK-NEXT: ldr w0, [x0, [[REG]]]
|
||||
; CHECK-NOT: uxtw
|
||||
%1 = sext i32 %b to i64
|
||||
%2 = add i64 %a, %1
|
||||
%3 = inttoptr i64 %2 to i32*
|
||||
%4 = load i32* %3
|
||||
%5 = zext i32 %4 to i64
|
||||
ret i64 %5
|
||||
}
|
||||
|
||||
define i32 @load_extend_sext_i8_to_i32(i64 %a, i32 %b) {
|
||||
; CHECK-LABEL: load_extend_sext_i8_to_i32
|
||||
; CHECK: sxtw [[REG:x[0-9]+]], w1
|
||||
; CHECK-NEXT: ldrsb w0, [x0, [[REG]]]
|
||||
; CHECK-NOT: sxtb
|
||||
%1 = sext i32 %b to i64
|
||||
%2 = add i64 %a, %1
|
||||
%3 = inttoptr i64 %2 to i8*
|
||||
%4 = load i8* %3
|
||||
%5 = sext i8 %4 to i32
|
||||
ret i32 %5
|
||||
}
|
||||
|
||||
define i32 @load_extend_sext_i16_to_i32(i64 %a, i32 %b) {
|
||||
; CHECK-LABEL: load_extend_sext_i16_to_i32
|
||||
; CHECK: sxtw [[REG:x[0-9]+]], w1
|
||||
; CHECK-NEXT: ldrsh w0, [x0, [[REG]]]
|
||||
; CHECK-NOT: sxth
|
||||
%1 = sext i32 %b to i64
|
||||
%2 = add i64 %a, %1
|
||||
%3 = inttoptr i64 %2 to i16*
|
||||
%4 = load i16* %3
|
||||
%5 = sext i16 %4 to i32
|
||||
ret i32 %5
|
||||
}
|
||||
|
||||
define i64 @load_extend_sext_i8_to_i64(i64 %a, i32 %b) {
|
||||
; CHECK-LABEL: load_extend_sext_i8_to_i64
|
||||
; CHECK: sxtw [[REG:x[0-9]+]], w1
|
||||
; CHECK-NEXT: ldrsb x0, [x0, [[REG]]]
|
||||
; CHECK-NOT: sxtb
|
||||
%1 = sext i32 %b to i64
|
||||
%2 = add i64 %a, %1
|
||||
%3 = inttoptr i64 %2 to i8*
|
||||
%4 = load i8* %3
|
||||
%5 = sext i8 %4 to i64
|
||||
ret i64 %5
|
||||
}
|
||||
|
||||
define i64 @load_extend_sext_i16_to_i64(i64 %a, i32 %b) {
|
||||
; CHECK-LABEL: load_extend_sext_i16_to_i64
|
||||
; CHECK: sxtw [[REG:x[0-9]+]], w1
|
||||
; CHECK-NEXT: ldrsh x0, [x0, [[REG]]]
|
||||
; CHECK-NOT: sxth
|
||||
%1 = sext i32 %b to i64
|
||||
%2 = add i64 %a, %1
|
||||
%3 = inttoptr i64 %2 to i16*
|
||||
%4 = load i16* %3
|
||||
%5 = sext i16 %4 to i64
|
||||
ret i64 %5
|
||||
}
|
||||
|
||||
define i64 @load_extend_sext_i32_to_i64(i64 %a, i32 %b) {
|
||||
; CHECK-LABEL: load_extend_sext_i32_to_i64
|
||||
; CHECK: sxtw [[REG:x[0-9]+]], w1
|
||||
; CHECK-NEXT: ldrsw x0, [x0, [[REG]]]
|
||||
; CHECK-NOT: sxtw
|
||||
%1 = sext i32 %b to i64
|
||||
%2 = add i64 %a, %1
|
||||
%3 = inttoptr i64 %2 to i32*
|
||||
%4 = load i32* %3
|
||||
%5 = sext i32 %4 to i64
|
||||
ret i64 %5
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue