Add MSP430 mem-mem insts support. Patch by Brian Lucas with some my refinements
llvm-svn: 83811
This commit is contained in:
Anton Korobeynikov
parent
2c2deae5ac
commit
415c3dc501
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@ -30,8 +30,12 @@
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/ADT/Statistic.h"
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using namespace llvm;
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STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor");
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/// MSP430DAGToDAGISel - MSP430 specific code to select MSP430 machine
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/// instructions for SelectionDAG operations.
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///
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@ -60,6 +64,7 @@ namespace {
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#include "MSP430GenDAGISel.inc"
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private:
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void PreprocessForRMW();
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SDNode *Select(SDValue Op);
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bool SelectAddr(SDValue Op, SDValue Addr, SDValue &Base, SDValue &Disp);
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@ -143,9 +148,131 @@ SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
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return false;
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}
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/// MoveBelowTokenFactor - Replace TokenFactor operand with load's chain operand
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/// and move load below the TokenFactor. Replace store's chain operand with
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/// load's chain result.
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/// Shamelessly stolen from X86.
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static void MoveBelowTokenFactor(SelectionDAG *CurDAG, SDValue Load,
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SDValue Store, SDValue TF) {
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SmallVector<SDValue, 4> Ops;
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bool isRMW = false;
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SDValue TF0, TF1, NewTF;
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for (unsigned i = 0, e = TF.getNode()->getNumOperands(); i != e; ++i)
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if (Load.getNode() == TF.getOperand(i).getNode()) {
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TF0 = Load.getOperand(0);
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Ops.push_back(TF0);
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} else {
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TF1 = TF.getOperand(i);
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Ops.push_back(TF1);
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if (LoadSDNode* LD = dyn_cast<LoadSDNode>(TF1))
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isRMW = !LD->isVolatile();
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}
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if (isRMW && TF1.getOperand(0).getNode() == TF0.getNode())
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NewTF = TF0;
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else
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NewTF = CurDAG->UpdateNodeOperands(TF, &Ops[0], Ops.size());
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SDValue NewLoad = CurDAG->UpdateNodeOperands(Load, NewTF,
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Load.getOperand(1),
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Load.getOperand(2));
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CurDAG->UpdateNodeOperands(Store, NewLoad.getValue(1), Store.getOperand(1),
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Store.getOperand(2), Store.getOperand(3));
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}
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/// isRMWLoad - Return true if N is a load that's part of RMW sub-DAG. The chain
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/// produced by the load must only be used by the store's chain operand,
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/// otherwise this may produce a cycle in the DAG.
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/// Shamelessly stolen from X86. FIXME: Should we make this function common?
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static bool isRMWLoad(SDValue N, SDValue Chain, SDValue Address,
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SDValue &Load) {
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if (N.getOpcode() == ISD::BIT_CONVERT)
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N = N.getOperand(0);
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LoadSDNode *LD = dyn_cast<LoadSDNode>(N);
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if (!LD || LD->isVolatile())
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return false;
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if (LD->getAddressingMode() != ISD::UNINDEXED)
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return false;
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ISD::LoadExtType ExtType = LD->getExtensionType();
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if (ExtType != ISD::NON_EXTLOAD && ExtType != ISD::EXTLOAD)
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return false;
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if (N.hasOneUse() &&
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LD->hasNUsesOfValue(1, 1) &&
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N.getOperand(1) == Address &&
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LD->isOperandOf(Chain.getNode())) {
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Load = N;
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return true;
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}
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return false;
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}
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/// PreprocessForRMW - Preprocess the DAG to make instruction selection better.
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/// Shamelessly stolen from X86.
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void MSP430DAGToDAGISel::PreprocessForRMW() {
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for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
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E = CurDAG->allnodes_end(); I != E; ++I) {
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if (!ISD::isNON_TRUNCStore(I))
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continue;
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SDValue Chain = I->getOperand(0);
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if (Chain.getNode()->getOpcode() != ISD::TokenFactor)
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continue;
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SDValue N1 = I->getOperand(1); // Value to store
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SDValue N2 = I->getOperand(2); // Address of store
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if (!N1.hasOneUse())
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continue;
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bool RModW = false;
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SDValue Load;
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unsigned Opcode = N1.getNode()->getOpcode();
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switch (Opcode) {
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case ISD::ADD:
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case ISD::AND:
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case ISD::OR:
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case ISD::XOR:
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case ISD::ADDC:
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case ISD::ADDE: {
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SDValue N10 = N1.getOperand(0);
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SDValue N11 = N1.getOperand(1);
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RModW = isRMWLoad(N10, Chain, N2, Load);
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if (!RModW && isRMWLoad(N11, Chain, N2, Load)) {
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// Swap the operands, making the RMW load the first operand seems
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// to help selection and prevent token chain loops.
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N1 = CurDAG->UpdateNodeOperands(N1, N11, N10);
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RModW = true;
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}
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break;
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}
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case ISD::SUB:
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case ISD::SUBC:
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case ISD::SUBE: {
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SDValue N10 = N1.getOperand(0);
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RModW = isRMWLoad(N10, Chain, N2, Load);
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break;
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}
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}
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if (RModW) {
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MoveBelowTokenFactor(CurDAG, Load, SDValue(I, 0), Chain);
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++NumLoadMoved;
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}
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}
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}
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/// InstructionSelect - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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void MSP430DAGToDAGISel::InstructionSelect() {
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PreprocessForRMW();
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DEBUG(errs() << "Selection DAG after RMW preprocessing:\n");
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DEBUG(CurDAG->dump());
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DEBUG(BB->dump());
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// Codegen the basic block.
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@ -0,0 +1,46 @@
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; RUN: llvm-as < %s | llc -march=msp430 | FileCheck %s
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target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
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target triple = "msp430-generic-generic"
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@foo = common global i16 0, align 2
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@bar = common global i16 0, align 2
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define void @add() nounwind {
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; CHECK: add:
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; CHECK: add.w &bar, &foo
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%1 = load i16* @bar
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%2 = load i16* @foo
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%3 = add i16 %2, %1
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store i16 %3, i16* @foo
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ret void
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}
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define void @and() nounwind {
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; CHECK: and:
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; CHECK: and.w &bar, &foo
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%1 = load i16* @bar
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%2 = load i16* @foo
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%3 = and i16 %2, %1
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store i16 %3, i16* @foo
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ret void
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}
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define void @bis() nounwind {
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; CHECK: bis:
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; CHECK: bis.w &bar, &foo
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%1 = load i16* @bar
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%2 = load i16* @foo
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%3 = or i16 %2, %1
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store i16 %3, i16* @foo
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ret void
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}
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define void @xor() nounwind {
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; CHECK: xor:
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; CHECK: xor.w &bar, &foo
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%1 = load i16* @bar
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%2 = load i16* @foo
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%3 = xor i16 %2, %1
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store i16 %3, i16* @foo
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ret void
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}
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@ -0,0 +1,47 @@
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; RUN: llvm-as < %s | llc -march=msp430 | FileCheck %s
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target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
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target triple = "msp430-generic-generic"
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@foo = common global i8 0, align 1
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@bar = common global i8 0, align 1
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define void @add() nounwind {
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; CHECK: add:
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; CHECK: add.b &bar, &foo
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%1 = load i8* @bar
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%2 = load i8* @foo
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%3 = add i8 %2, %1
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store i8 %3, i8* @foo
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ret void
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}
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define void @and() nounwind {
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; CHECK: and:
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; CHECK: and.b &bar, &foo
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%1 = load i8* @bar
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%2 = load i8* @foo
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%3 = and i8 %2, %1
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store i8 %3, i8* @foo
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ret void
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}
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define void @bis() nounwind {
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; CHECK: bis:
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; CHECK: bis.b &bar, &foo
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%1 = load i8* @bar
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%2 = load i8* @foo
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%3 = or i8 %2, %1
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store i8 %3, i8* @foo
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ret void
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}
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define void @xor() nounwind {
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; CHECK: xor:
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; CHECK: xor.b &bar, &foo
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%1 = load i8* @bar
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%2 = load i8* @foo
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%3 = xor i8 %2, %1
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store i8 %3, i8* @foo
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ret void
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}
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