replica
/
hanchenye-llvm-project
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Add assembler/disassembler support for non-AVX pclmulqdq. While I'm here, use proper aliases for the pclmullqlqdq and friends. PR10269. 

llvm-svn: 134424
This commit is contained in:
Eli Friedman 2011-07-05 18:21:20 +00:00
parent 92905a1767
commit 415412e82f
4 changed files with 56 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
View File

@ -710,23 +710,6 @@ ParseInstruction(StringRef Name, SMLoc NameLoc,
}
}
// FIXME: Hack to recognize vpclmul<src1_quadword, src2_quadword>dq
if (PatchedName.startswith("vpclmul")) {
unsigned CLMULQuadWordSelect = StringSwitch<unsigned>(
PatchedName.slice(7, PatchedName.size() - 2))
.Case("lqlq", 0x00) // src1[63:0], src2[63:0]
.Case("hqlq", 0x01) // src1[127:64], src2[63:0]
.Case("lqhq", 0x10) // src1[63:0], src2[127:64]
.Case("hqhq", 0x11) // src1[127:64], src2[127:64]
.Default(~0U);
if (CLMULQuadWordSelect != ~0U) {
ExtraImmOp = MCConstantExpr::Create(CLMULQuadWordSelect,
getParser().getContext());
assert(PatchedName.endswith("dq") && "Unexpected mnemonic!");
PatchedName = "vpclmulqdq";
}
}
Operands.push_back(X86Operand::CreateToken(PatchedName, NameLoc));
if (ExtraImmOp)

5
llvm/lib/Target/X86/X86InstrFormats.td
View File

@ -459,6 +459,11 @@ class AESAI<bits<8> o, Format F, dag outs, dag ins, string asm,
// CLMUL Instruction Templates
class CLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag>pattern>
: Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
OpSize, Requires<[HasCLMUL]>;
class AVXCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag>pattern>
: Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
OpSize, VEX_4V, Requires<[HasAVX, HasCLMUL]>;

51
llvm/lib/Target/X86/X86InstrSSE.td
View File

@ -5195,33 +5195,52 @@ def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
// CLMUL Instructions
//===----------------------------------------------------------------------===//
// Only the AVX version of CLMUL instructions are described here.
// Carry-less Multiplication instructions
def VPCLMULQDQrr : CLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
let Constraints = "$src1 = $dst" in {
def PCLMULQDQrr : CLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
(ins VR128:$src1, VR128:$src2, i8imm:$src3),
"pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
[]>;
def PCLMULQDQrm : CLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
(ins VR128:$src1, i128mem:$src2, i8imm:$src3),
"pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
[]>;
}
// AVX carry-less Multiplication instructions
def VPCLMULQDQrr : AVXCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
(ins VR128:$src1, VR128:$src2, i8imm:$src3),
"vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
[]>;
def VPCLMULQDQrm : CLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
def VPCLMULQDQrm : AVXCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
(ins VR128:$src1, i128mem:$src2, i8imm:$src3),
"vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
[]>;
// Assembler Only
multiclass avx_vpclmul<string asm> {
def rr : I<0, Pseudo, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
!strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[]>;
def rm : I<0, Pseudo, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
!strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[]>;
multiclass pclmul_alias<string asm, int immop> {
def : InstAlias<!strconcat("pclmul", asm,
"dq {$src, $dst|$dst, $src}"),
(PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
def : InstAlias<!strconcat("pclmul", asm,
"dq {$src, $dst|$dst, $src}"),
(PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
def : InstAlias<!strconcat("vpclmul", asm,
"dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
(VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
def : InstAlias<!strconcat("vpclmul", asm,
"dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
(VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
}
defm VPCLMULHQHQDQ : avx_vpclmul<"vpclmulhqhqdq">;
defm VPCLMULHQLQDQ : avx_vpclmul<"vpclmulhqlqdq">;
defm VPCLMULLQHQDQ : avx_vpclmul<"vpclmullqhqdq">;
defm VPCLMULLQLQDQ : avx_vpclmul<"vpclmullqlqdq">;
defm : pclmul_alias<"hqhq", 0x11>;
defm : pclmul_alias<"hqlq", 0x01>;
defm : pclmul_alias<"lqhq", 0x10>;
defm : pclmul_alias<"lqlq", 0x00>;
//===----------------------------------------------------------------------===//
// AVX Instructions

16
llvm/test/MC/X86/x86-64.s
View File

@ -1148,3 +1148,19 @@ movnti %eax, (%rdi)
// CHECK: movntiq
movntiq %rax, (%rdi)
movnti %rax, (%rdi)
// CHECK: pclmulqdq $17, %xmm0, %xmm1
// CHECK: encoding: [0x66,0x0f,0x3a,0x44,0xc8,0x11]
pclmulhqhqdq %xmm0, %xmm1
// CHECK: pclmulqdq $1, %xmm0, %xmm1
// CHECK: encoding: [0x66,0x0f,0x3a,0x44,0xc8,0x01]
pclmulqdq $1, %xmm0, %xmm1
// CHECK: pclmulqdq $16, (%rdi), %xmm1
// CHECK: encoding: [0x66,0x0f,0x3a,0x44,0x0f,0x10]
pclmullqhqdq (%rdi), %xmm1
// CHECK: pclmulqdq $0, (%rdi), %xmm1
// CHECK: encoding: [0x66,0x0f,0x3a,0x44,0x0f,0x00]
pclmulqdq $0, (%rdi), %xmm1