Allow more cases of undef shuffle indices and add tests for them.
llvm-svn: 111226
This commit is contained in:
Bob Wilson
parent
8b637b177c
commit
411dfad981
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@ -3148,6 +3148,11 @@ static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT,
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bool &ReverseVEXT, unsigned &Imm) {
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unsigned NumElts = VT.getVectorNumElements();
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ReverseVEXT = false;
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// Assume that the first shuffle index is not UNDEF. Fail if it is.
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if (M[0] < 0)
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return false;
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Imm = M[0];
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// If this is a VEXT shuffle, the immediate value is the index of the first
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@ -3163,6 +3168,7 @@ static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT,
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ReverseVEXT = true;
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}
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if (M[i] < 0) continue; // ignore UNDEF indices
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if (ExpectedElt != static_cast<unsigned>(M[i]))
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return false;
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}
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@ -3188,13 +3194,16 @@ static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT,
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unsigned NumElts = VT.getVectorNumElements();
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unsigned BlockElts = M[0] + 1;
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// If the first shuffle index is UNDEF, be optimistic.
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if (M[0] < 0)
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BlockElts = BlockSize / EltSz;
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if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
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return false;
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for (unsigned i = 0; i < NumElts; ++i) {
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if ((unsigned) M[i] !=
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(i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
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if (M[i] < 0) continue; // ignore UNDEF indices
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if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
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return false;
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}
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@ -3210,8 +3219,8 @@ static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT,
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unsigned NumElts = VT.getVectorNumElements();
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WhichResult = (M[0] == 0 ? 0 : 1);
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for (unsigned i = 0; i < NumElts; i += 2) {
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if ((unsigned) M[i] != i + WhichResult ||
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(unsigned) M[i+1] != i + NumElts + WhichResult)
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if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
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(M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult))
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return false;
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}
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return true;
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@ -3229,9 +3238,8 @@ static bool isVTRN_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
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unsigned NumElts = VT.getVectorNumElements();
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WhichResult = (M[0] == 0 ? 0 : 1);
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for (unsigned i = 0; i < NumElts; i += 2) {
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if (M[i] < 0) continue;
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if ((unsigned) M[i] != i + WhichResult ||
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(unsigned) M[i+1] != i + WhichResult)
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if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
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(M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult))
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return false;
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}
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return true;
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@ -3246,6 +3254,7 @@ static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT,
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unsigned NumElts = VT.getVectorNumElements();
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WhichResult = (M[0] == 0 ? 0 : 1);
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for (unsigned i = 0; i != NumElts; ++i) {
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if (M[i] < 0) continue; // ignore UNDEF indices
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if ((unsigned) M[i] != 2 * i + WhichResult)
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return false;
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}
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@ -3271,7 +3280,8 @@ static bool isVUZP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
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for (unsigned j = 0; j != 2; ++j) {
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unsigned Idx = WhichResult;
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for (unsigned i = 0; i != Half; ++i) {
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if ((unsigned) M[i + j * Half] != Idx)
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int MIdx = M[i + j * Half];
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if (MIdx >= 0 && (unsigned) MIdx != Idx)
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return false;
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Idx += 2;
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}
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@ -3294,8 +3304,8 @@ static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT,
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WhichResult = (M[0] == 0 ? 0 : 1);
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unsigned Idx = WhichResult * NumElts / 2;
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for (unsigned i = 0; i != NumElts; i += 2) {
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if ((unsigned) M[i] != Idx ||
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(unsigned) M[i+1] != Idx + NumElts)
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if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
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(M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts))
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return false;
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Idx += 1;
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}
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@ -3320,8 +3330,8 @@ static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
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WhichResult = (M[0] == 0 ? 0 : 1);
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unsigned Idx = WhichResult * NumElts / 2;
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for (unsigned i = 0; i != NumElts; i += 2) {
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if ((unsigned) M[i] != Idx ||
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(unsigned) M[i+1] != Idx)
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if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
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(M[i+1] >= 0 && (unsigned) M[i+1] != Idx))
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return false;
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Idx += 1;
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}
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@ -54,3 +54,23 @@ define <4 x i32> @test_vextq32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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ret <4 x i32> %tmp3
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}
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; Undef shuffle indices should not prevent matching to VEXT:
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define <8 x i8> @test_vextd_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK: test_vextd_undef:
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;CHECK: vext
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 3, i32 undef, i32 undef, i32 6, i32 7, i32 8, i32 9, i32 10>
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ret <8 x i8> %tmp3
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}
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define <16 x i8> @test_vextRq_undef(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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;CHECK: test_vextRq_undef:
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;CHECK: vext
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%tmp1 = load <16 x i8>* %A
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%tmp2 = load <16 x i8>* %B
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%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 23, i32 24, i32 25, i32 26, i32 undef, i32 undef, i32 29, i32 30, i32 31, i32 0, i32 1, i32 2, i32 3, i32 4, i32 undef, i32 6>
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ret <16 x i8> %tmp3
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}
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@ -111,3 +111,21 @@ define <16 x i8> @test_vrev16Q8(<16 x i8>* %A) nounwind {
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%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
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ret <16 x i8> %tmp2
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}
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; Undef shuffle indices should not prevent matching to VREV:
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define <8 x i8> @test_vrev64D8_undef(<8 x i8>* %A) nounwind {
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;CHECK: test_vrev64D8_undef:
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;CHECK: vrev64.8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 undef, i32 undef, i32 4, i32 3, i32 2, i32 1, i32 0>
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ret <8 x i8> %tmp2
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}
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define <8 x i16> @test_vrev32Q16_undef(<8 x i16>* %A) nounwind {
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;CHECK: test_vrev32Q16_undef:
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;CHECK: vrev32.16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 undef, i32 0, i32 undef, i32 2, i32 5, i32 4, i32 7, i32 undef>
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ret <8 x i16> %tmp2
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}
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@ -95,3 +95,30 @@ define <4 x float> @vtrnQf(<4 x float>* %A, <4 x float>* %B) nounwind {
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%tmp5 = fadd <4 x float> %tmp3, %tmp4
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ret <4 x float> %tmp5
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}
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; Undef shuffle indices should not prevent matching to VTRN:
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define <8 x i8> @vtrni8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK: vtrni8_undef:
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;CHECK: vtrn.8
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;CHECK-NEXT: vadd.i8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 undef, i32 2, i32 10, i32 undef, i32 12, i32 6, i32 14>
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%tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 undef, i32 undef, i32 15>
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%tmp5 = add <8 x i8> %tmp3, %tmp4
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ret <8 x i8> %tmp5
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}
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define <8 x i16> @vtrnQi16_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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;CHECK: vtrnQi16_undef:
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;CHECK: vtrn.16
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;CHECK-NEXT: vadd.i16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i16>* %B
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%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 undef, i32 undef, i32 4, i32 12, i32 6, i32 14>
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%tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 undef, i32 3, i32 11, i32 5, i32 13, i32 undef, i32 undef>
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%tmp5 = add <8 x i16> %tmp3, %tmp4
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ret <8 x i16> %tmp5
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}
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@ -73,3 +73,30 @@ define <4 x float> @vuzpQf(<4 x float>* %A, <4 x float>* %B) nounwind {
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%tmp5 = fadd <4 x float> %tmp3, %tmp4
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ret <4 x float> %tmp5
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}
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; Undef shuffle indices should not prevent matching to VUZP:
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define <8 x i8> @vuzpi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK: vuzpi8_undef:
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;CHECK: vuzp.8
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;CHECK-NEXT: vadd.i8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 2, i32 undef, i32 undef, i32 8, i32 10, i32 12, i32 14>
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%tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 undef, i32 undef, i32 13, i32 15>
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%tmp5 = add <8 x i8> %tmp3, %tmp4
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ret <8 x i8> %tmp5
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}
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define <8 x i16> @vuzpQi16_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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;CHECK: vuzpQi16_undef:
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;CHECK: vuzp.16
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;CHECK-NEXT: vadd.i16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i16>* %B
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%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 undef, i32 4, i32 undef, i32 8, i32 10, i32 12, i32 14>
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%tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 undef, i32 undef, i32 11, i32 13, i32 15>
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%tmp5 = add <8 x i16> %tmp3, %tmp4
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ret <8 x i16> %tmp5
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}
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@ -73,3 +73,30 @@ define <4 x float> @vzipQf(<4 x float>* %A, <4 x float>* %B) nounwind {
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%tmp5 = fadd <4 x float> %tmp3, %tmp4
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ret <4 x float> %tmp5
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}
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; Undef shuffle indices should not prevent matching to VZIP:
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define <8 x i8> @vzipi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK: vzipi8_undef:
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;CHECK: vzip.8
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;CHECK-NEXT: vadd.i8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 undef, i32 1, i32 9, i32 undef, i32 10, i32 3, i32 11>
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%tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 undef, i32 undef, i32 15>
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%tmp5 = add <8 x i8> %tmp3, %tmp4
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ret <8 x i8> %tmp5
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}
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define <16 x i8> @vzipQi8_undef(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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;CHECK: vzipQi8_undef:
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;CHECK: vzip.8
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;CHECK-NEXT: vadd.i8
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%tmp1 = load <16 x i8>* %A
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%tmp2 = load <16 x i8>* %B
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%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 1, i32 undef, i32 undef, i32 undef, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
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%tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 24, i32 9, i32 undef, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 undef, i32 14, i32 30, i32 undef, i32 31>
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%tmp5 = add <16 x i8> %tmp3, %tmp4
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ret <16 x i8> %tmp5
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}
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