[Pipeliner] Enable more base+offset dependence changes in pipeliner
The pipeliner changes dependences between base+offset instructions (loads and stores) so that the instructions have more flexibility to be scheduled with respect to each other. This occurs when the pipeliner is able to compute that the instructions will not alias if their order is changed. The prevous code enforced the alias property by checking if the base register is the same, and that the offset values are either both positive or negative. This patch improves the alias check by using the API areMemAccessesTriviallyDisjoint instead. This enables more cases, especially if the offset is a negative value. The pipeliner uses the function by creating a new instruction with the offset used in the next iteration. Patch by Brendon Cahoon. llvm-svn: 328538
This commit is contained in:
parent
55cb4986a4
commit
40df8a2b98
|
@ -3454,10 +3454,15 @@ bool SwingSchedulerDAG::canUseLastOffsetValue(MachineInstr *MI,
|
|||
if (!TII->getBaseAndOffsetPosition(*PrevDef, BasePos1, OffsetPos1))
|
||||
return false;
|
||||
|
||||
// Make sure offset values are both positive or both negative.
|
||||
// Make sure that the instructions do not access the same memory location in
|
||||
// the next iteration.
|
||||
int64_t LoadOffset = MI->getOperand(OffsetPosLd).getImm();
|
||||
int64_t StoreOffset = PrevDef->getOperand(OffsetPos1).getImm();
|
||||
if ((LoadOffset >= 0) != (StoreOffset >= 0))
|
||||
MachineInstr *NewMI = MF.CloneMachineInstr(MI);
|
||||
NewMI->getOperand(OffsetPosLd).setImm(LoadOffset + StoreOffset);
|
||||
bool Disjoint = TII->areMemAccessesTriviallyDisjoint(*NewMI, *PrevDef);
|
||||
MF.DeleteMachineInstr(NewMI);
|
||||
if (!Disjoint)
|
||||
return false;
|
||||
|
||||
// Set the return value once we determine that we return true.
|
||||
|
|
Loading…
Reference in New Issue