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Fix a truly heinous bug in DAGCombine related to AssertZext. 

If we have a chain of zext -> assert_zext -> zext -> use, the first zext would get simplified away because of the later zext, and then the later zext would get simplified away because of the assert.  The solution is to teach SimplifyDemandedBits that assert_zext demands all of the high bits of its input, rather than only those demanded by its users.  No testcase because the only example I have manifests as llvm-gcc miscompiling LLVM, and I haven't found a smaller case that reproduces this problem.
Fixes <rdar://problem/10063365>.

llvm-svn: 139059
This commit is contained in:
Owen Anderson 2011-09-03 00:26:49 +00:00
parent 5423017526
commit 40d756eacc
1 changed files with 6 additions and 7 deletions
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13
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
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@ -1765,17 +1765,16 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
break;
}
case ISD::AssertZext: {
// Demand all the bits of the input that are demanded in the output.
// The low bits are obvious; the high bits are demanded because we're
// asserting that they're zero here.
if (SimplifyDemandedBits(Op.getOperand(0), NewMask,
// AssertZext demands all of the high bits, plus any of the low bits
// demanded by its users.
EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
APInt InMask = APInt::getLowBitsSet(BitWidth,
VT.getSizeInBits());
if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask,
KnownZero, KnownOne, TLO, Depth+1))
return true;
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
APInt InMask = APInt::getLowBitsSet(BitWidth,
VT.getSizeInBits());
KnownZero |= ~InMask & NewMask;
break;
}