More constification of things. More comments added. No functionality
changes. (Sorry for any formatting changes that creeped in.) llvm-svn: 47362
This commit is contained in:
parent
b0a2f9513f
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406fdbd3ad
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@ -137,8 +137,8 @@ private: // Intermediate data structures
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// register references as presumed dead across basic blocks.
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// register references as presumed dead across basic blocks.
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MachineInstr **PhysRegInfo;
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MachineInstr **PhysRegInfo;
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// PhysRegUsed - Keep track whether the physical register has been used after
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// PhysRegUsed - Keep track of whether the physical register has been used
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// its last definition. This is local property.
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// after its last definition. This is local property.
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bool *PhysRegUsed;
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bool *PhysRegUsed;
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// PhysRegPartUse - Keep track of which instruction was the last partial use
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// PhysRegPartUse - Keep track of which instruction was the last partial use
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@ -160,7 +160,7 @@ private: // Intermediate data structures
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/// HandlePhysRegKill - Add kills of Reg and its sub-registers to the
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/// HandlePhysRegKill - Add kills of Reg and its sub-registers to the
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/// uses. Pay special attention to the sub-register uses which may come below
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/// uses. Pay special attention to the sub-register uses which may come below
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/// the last use of the whole register.
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/// the last use of the whole register.
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bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI,
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bool HandlePhysRegKill(unsigned Reg, const MachineInstr *MI,
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SmallSet<unsigned, 4> &SubKills);
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SmallSet<unsigned, 4> &SubKills);
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bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI);
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bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI);
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void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
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void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
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@ -153,6 +153,7 @@ void LiveVariables::MarkVirtRegAliveInBlock(VarInfo& VRInfo,
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MachineBasicBlock *MBB) {
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MachineBasicBlock *MBB) {
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std::vector<MachineBasicBlock*> WorkList;
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std::vector<MachineBasicBlock*> WorkList;
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MarkVirtRegAliveInBlock(VRInfo, DefBlock, MBB, WorkList);
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MarkVirtRegAliveInBlock(VRInfo, DefBlock, MBB, WorkList);
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while (!WorkList.empty()) {
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while (!WorkList.empty()) {
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MachineBasicBlock *Pred = WorkList.back();
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MachineBasicBlock *Pred = WorkList.back();
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WorkList.pop_back();
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WorkList.pop_back();
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@ -163,7 +164,7 @@ void LiveVariables::MarkVirtRegAliveInBlock(VarInfo& VRInfo,
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void LiveVariables::HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
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void LiveVariables::HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
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MachineInstr *MI) {
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MachineInstr *MI) {
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MachineRegisterInfo& MRI = MBB->getParent()->getRegInfo();
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const MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
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assert(MRI.getVRegDef(reg) && "Register use before def!");
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assert(MRI.getVRegDef(reg) && "Register use before def!");
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unsigned BBNum = MBB->getNumber();
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unsigned BBNum = MBB->getNumber();
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@ -194,7 +195,7 @@ void LiveVariables::HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
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if (!VRInfo.AliveBlocks[BBNum])
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if (!VRInfo.AliveBlocks[BBNum])
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VRInfo.Kills.push_back(MI);
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VRInfo.Kills.push_back(MI);
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// Update all dominating blocks to mark them known live.
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// Update all dominating blocks to mark them as "known live".
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for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
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for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
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E = MBB->pred_end(); PI != E; ++PI)
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E = MBB->pred_end(); PI != E; ++PI)
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MarkVirtRegAliveInBlock(VRInfo, MRI.getVRegDef(reg)->getParent(), *PI);
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MarkVirtRegAliveInBlock(VRInfo, MRI.getVRegDef(reg)->getParent(), *PI);
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@ -256,50 +257,71 @@ void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
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}
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}
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}
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}
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bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *RefMI,
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/// addRegisterKills - For all of a register's sub-registers that are killed in
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/// other instructions (?), indicate that they are killed in this machine
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/// instruction by marking the operand as "killed". (If the machine operand
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/// isn't found, add it first.)
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void LiveVariables::addRegisterKills(unsigned Reg, MachineInstr *MI,
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SmallSet<unsigned, 4> &SubKills) {
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SmallSet<unsigned, 4> &SubKills) {
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if (SubKills.count(Reg) == 0) {
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MI->addRegisterKilled(Reg, RegInfo, true);
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return;
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}
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for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg);
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for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg);
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unsigned SubReg = *SubRegs; ++SubRegs) {
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unsigned SubReg = *SubRegs; ++SubRegs)
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MachineInstr *LastRef = PhysRegInfo[SubReg];
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addRegisterKills(SubReg, MI, SubKills);
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}
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/// HandlePhysRegKill - The recursive version of HandlePhysRegKill. Returns true
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/// if:
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///
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/// - The register has no sub-registers and the machine instruction is the
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/// last def/use of the register, or
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/// - The register has sub-registers and none of them are killed elsewhere.
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///
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bool LiveVariables::HandlePhysRegKill(unsigned Reg, const MachineInstr *RefMI,
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SmallSet<unsigned, 4> &SubKills) {
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const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg);
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for (; unsigned SubReg = *SubRegs; ++SubRegs) {
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const MachineInstr *LastRef = PhysRegInfo[SubReg];
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if (LastRef != RefMI ||
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if (LastRef != RefMI ||
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!HandlePhysRegKill(SubReg, RefMI, SubKills))
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!HandlePhysRegKill(SubReg, RefMI, SubKills))
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SubKills.insert(SubReg);
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SubKills.insert(SubReg);
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}
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}
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if (*RegInfo->getImmediateSubRegisters(Reg) == 0) {
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if (*SubRegs == 0) {
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// No sub-registers, just check if reg is killed by RefMI.
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// No sub-registers, just check if reg is killed by RefMI.
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if (PhysRegInfo[Reg] == RefMI)
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if (PhysRegInfo[Reg] == RefMI)
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return true;
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return true;
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} else if (SubKills.empty())
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} else if (SubKills.empty()) {
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// None of the sub-registers are killed elsewhere...
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// None of the sub-registers are killed elsewhere.
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return true;
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return true;
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}
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return false;
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return false;
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}
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}
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void LiveVariables::addRegisterKills(unsigned Reg, MachineInstr *MI,
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/// HandlePhysRegKill - Calls the recursive version of HandlePhysRegKill. (See
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SmallSet<unsigned, 4> &SubKills) {
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/// above for details.)
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if (SubKills.count(Reg) == 0)
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MI->addRegisterKilled(Reg, RegInfo, true);
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else {
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for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg);
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unsigned SubReg = *SubRegs; ++SubRegs)
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addRegisterKills(SubReg, MI, SubKills);
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}
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}
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bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *RefMI) {
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bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *RefMI) {
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SmallSet<unsigned, 4> SubKills;
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SmallSet<unsigned, 4> SubKills;
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if (HandlePhysRegKill(Reg, RefMI, SubKills)) {
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if (HandlePhysRegKill(Reg, RefMI, SubKills)) {
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// This machine instruction kills this register.
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RefMI->addRegisterKilled(Reg, RegInfo, true);
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RefMI->addRegisterKilled(Reg, RegInfo, true);
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return true;
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return true;
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} else {
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}
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// Some sub-registers are killed by another MI.
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// Some sub-registers are killed by another machine instruction.
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for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg);
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for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg);
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unsigned SubReg = *SubRegs; ++SubRegs)
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unsigned SubReg = *SubRegs; ++SubRegs)
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addRegisterKills(SubReg, RefMI, SubKills);
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addRegisterKills(SubReg, RefMI, SubKills);
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return false;
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return false;
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}
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}
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}
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void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) {
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void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) {
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// Does this kill a previous version of this register?
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// Does this kill a previous version of this register?
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@ -309,14 +331,15 @@ void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) {
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if (PhysRegPartUse[Reg])
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if (PhysRegPartUse[Reg])
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PhysRegPartUse[Reg]->addRegisterKilled(Reg, RegInfo, true);
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PhysRegPartUse[Reg]->addRegisterKilled(Reg, RegInfo, true);
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}
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}
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} else if (PhysRegPartUse[Reg])
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} else if (PhysRegPartUse[Reg]) {
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// Add implicit use / kill to last partial use.
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// Add implicit use / kill to last partial use.
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PhysRegPartUse[Reg]->addRegisterKilled(Reg, RegInfo, true);
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PhysRegPartUse[Reg]->addRegisterKilled(Reg, RegInfo, true);
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else if (LastRef != MI)
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} else if (LastRef != MI) {
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// Defined, but not used. However, watch out for cases where a super-reg
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// Defined, but not used. However, watch out for cases where a super-reg
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// is also defined on the same MI.
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// is also defined on the same MI.
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LastRef->addRegisterDead(Reg, RegInfo);
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LastRef->addRegisterDead(Reg, RegInfo);
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}
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}
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}
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for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
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for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
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unsigned SubReg = *SubRegs; ++SubRegs) {
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unsigned SubReg = *SubRegs; ++SubRegs) {
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@ -326,14 +349,15 @@ void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) {
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if (PhysRegPartUse[SubReg])
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if (PhysRegPartUse[SubReg])
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PhysRegPartUse[SubReg]->addRegisterKilled(SubReg, RegInfo, true);
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PhysRegPartUse[SubReg]->addRegisterKilled(SubReg, RegInfo, true);
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}
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}
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} else if (PhysRegPartUse[SubReg])
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} else if (PhysRegPartUse[SubReg]) {
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// Add implicit use / kill to last use of a sub-register.
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// Add implicit use / kill to last use of a sub-register.
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PhysRegPartUse[SubReg]->addRegisterKilled(SubReg, RegInfo, true);
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PhysRegPartUse[SubReg]->addRegisterKilled(SubReg, RegInfo, true);
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else if (LastRef != MI)
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} else if (LastRef != MI) {
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// This must be a def of the subreg on the same MI.
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// This must be a def of the subreg on the same MI.
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LastRef->addRegisterDead(SubReg, RegInfo);
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LastRef->addRegisterDead(SubReg, RegInfo);
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}
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}
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}
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}
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}
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if (MI) {
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if (MI) {
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for (const unsigned *SuperRegs = RegInfo->getSuperRegisters(Reg);
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for (const unsigned *SuperRegs = RegInfo->getSuperRegisters(Reg);
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@ -360,6 +384,7 @@ void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) {
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PhysRegUsed[Reg] = false;
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PhysRegUsed[Reg] = false;
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PhysRegPartDef[Reg].clear();
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PhysRegPartDef[Reg].clear();
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PhysRegPartUse[Reg] = NULL;
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PhysRegPartUse[Reg] = NULL;
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for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
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for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
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unsigned SubReg = *SubRegs; ++SubRegs) {
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unsigned SubReg = *SubRegs; ++SubRegs) {
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PhysRegInfo[SubReg] = MI;
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PhysRegInfo[SubReg] = MI;
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@ -429,8 +454,10 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
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// Process all uses...
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// Process all uses...
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for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
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for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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const MachineOperand &MO = MI->getOperand(i);
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if (MO.isRegister() && MO.isUse() && MO.getReg()) {
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if (MO.isRegister() && MO.isUse() && MO.getReg()) {
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unsigned MOReg = MO.getReg();
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unsigned MOReg = MO.getReg();
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if (TargetRegisterInfo::isVirtualRegister(MOReg))
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if (TargetRegisterInfo::isVirtualRegister(MOReg))
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HandleVirtRegUse(MOReg, MBB, MI);
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HandleVirtRegUse(MOReg, MBB, MI);
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else if (TargetRegisterInfo::isPhysicalRegister(MOReg) &&
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else if (TargetRegisterInfo::isPhysicalRegister(MOReg) &&
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@ -442,8 +469,10 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
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// Process all defs...
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// Process all defs...
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for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
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for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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const MachineOperand &MO = MI->getOperand(i);
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if (MO.isRegister() && MO.isDef() && MO.getReg()) {
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if (MO.isRegister() && MO.isDef() && MO.getReg()) {
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unsigned MOReg = MO.getReg();
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unsigned MOReg = MO.getReg();
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if (TargetRegisterInfo::isVirtualRegister(MOReg)) {
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if (TargetRegisterInfo::isVirtualRegister(MOReg)) {
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VarInfo &VRInfo = getVarInfo(MOReg);
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VarInfo &VRInfo = getVarInfo(MOReg);
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@ -466,23 +495,24 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
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SmallVector<unsigned, 4>& VarInfoVec = PHIVarInfo[MBB->getNumber()];
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SmallVector<unsigned, 4>& VarInfoVec = PHIVarInfo[MBB->getNumber()];
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for (SmallVector<unsigned, 4>::iterator I = VarInfoVec.begin(),
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for (SmallVector<unsigned, 4>::iterator I = VarInfoVec.begin(),
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E = VarInfoVec.end(); I != E; ++I) {
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E = VarInfoVec.end(); I != E; ++I)
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// Only mark it alive only in the block we are representing.
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// Mark it alive only in the block we are representing.
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MarkVirtRegAliveInBlock(getVarInfo(*I), MRI.getVRegDef(*I)->getParent(),
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MarkVirtRegAliveInBlock(getVarInfo(*I), MRI.getVRegDef(*I)->getParent(),
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MBB);
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MBB);
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}
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}
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}
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// Finally, if the last instruction in the block is a return, make sure to mark
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// Finally, if the last instruction in the block is a return, make sure to mark
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// it as using all of the live-out values in the function.
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// it as using all of the live-out values in the function.
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if (!MBB->empty() && MBB->back().getDesc().isReturn()) {
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if (!MBB->empty() && MBB->back().getDesc().isReturn()) {
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MachineInstr *Ret = &MBB->back();
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MachineInstr *Ret = &MBB->back();
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for (MachineRegisterInfo::liveout_iterator
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for (MachineRegisterInfo::liveout_iterator
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I = MF->getRegInfo().liveout_begin(),
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I = MF->getRegInfo().liveout_begin(),
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E = MF->getRegInfo().liveout_end(); I != E; ++I) {
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E = MF->getRegInfo().liveout_end(); I != E; ++I) {
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assert(TargetRegisterInfo::isPhysicalRegister(*I) &&
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assert(TargetRegisterInfo::isPhysicalRegister(*I) &&
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"Cannot have a live-in virtual register!");
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"Cannot have a live-in virtual register!");
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HandlePhysRegUse(*I, Ret);
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HandlePhysRegUse(*I, Ret);
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// Add live-out registers as implicit uses.
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// Add live-out registers as implicit uses.
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if (Ret->findRegisterUseOperandIdx(*I) == -1)
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if (Ret->findRegisterUseOperandIdx(*I) == -1)
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Ret->addOperand(MachineOperand::CreateReg(*I, false, true));
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Ret->addOperand(MachineOperand::CreateReg(*I, false, true));
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@ -498,6 +528,7 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
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// Clear some states between BB's. These are purely local information.
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// Clear some states between BB's. These are purely local information.
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for (unsigned i = 0; i != NumRegs; ++i)
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for (unsigned i = 0; i != NumRegs; ++i)
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PhysRegPartDef[i].clear();
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PhysRegPartDef[i].clear();
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std::fill(PhysRegInfo, PhysRegInfo + NumRegs, (MachineInstr*)0);
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std::fill(PhysRegInfo, PhysRegInfo + NumRegs, (MachineInstr*)0);
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std::fill(PhysRegUsed, PhysRegUsed + NumRegs, false);
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std::fill(PhysRegUsed, PhysRegUsed + NumRegs, false);
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std::fill(PhysRegPartUse, PhysRegPartUse + NumRegs, (MachineInstr*)0);
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std::fill(PhysRegPartUse, PhysRegPartUse + NumRegs, (MachineInstr*)0);
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@ -507,17 +538,18 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
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// VirtRegInfo onto MI's.
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// VirtRegInfo onto MI's.
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//
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//
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for (unsigned i = 0, e1 = VirtRegInfo.size(); i != e1; ++i)
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for (unsigned i = 0, e1 = VirtRegInfo.size(); i != e1; ++i)
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for (unsigned j = 0, e2 = VirtRegInfo[i].Kills.size(); j != e2; ++j) {
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for (unsigned j = 0, e2 = VirtRegInfo[i].Kills.size(); j != e2; ++j)
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if (VirtRegInfo[i].Kills[j] == MRI.getVRegDef(i +
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if (VirtRegInfo[i].Kills[j] ==
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TargetRegisterInfo::FirstVirtualRegister))
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MRI.getVRegDef(i + TargetRegisterInfo::FirstVirtualRegister))
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VirtRegInfo[i].Kills[j]->addRegisterDead(i +
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VirtRegInfo[i]
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.Kills[j]->addRegisterDead(i +
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TargetRegisterInfo::FirstVirtualRegister,
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TargetRegisterInfo::FirstVirtualRegister,
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RegInfo);
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RegInfo);
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else
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else
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VirtRegInfo[i].Kills[j]->addRegisterKilled(i +
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VirtRegInfo[i]
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.Kills[j]->addRegisterKilled(i +
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TargetRegisterInfo::FirstVirtualRegister,
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TargetRegisterInfo::FirstVirtualRegister,
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RegInfo);
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RegInfo);
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}
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// Check to make sure there are no unreachable blocks in the MC CFG for the
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// Check to make sure there are no unreachable blocks in the MC CFG for the
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// function. If so, it is due to a bug in the instruction selector or some
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// function. If so, it is due to a bug in the instruction selector or some
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