parent
55ddc30f07
commit
406f270148
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@ -411,10 +411,9 @@ void MachineInstr::addImplicitDefUseOperands() {
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addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
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addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
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}
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}
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/// MachineInstr ctor - This constructor create a MachineInstr and add the
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/// MachineInstr ctor - This constructor creates a MachineInstr and adds the
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/// implicit operands. It reserves space for number of operands specified by
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/// implicit operands. It reserves space for the number of operands specified by
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/// TargetInstrDesc or the numOperands if it is not zero. (for
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/// the TargetInstrDesc.
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/// instructions with variable number of operands).
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MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
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MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
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: TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0),
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: TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0),
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MemRefs(0), MemRefsEnd(0), Parent(0) {
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MemRefs(0), MemRefsEnd(0), Parent(0) {
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@ -452,7 +451,6 @@ MachineInstr::MachineInstr(const TargetInstrDesc &tid, const DebugLoc dl,
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/// MachineInstr ctor - Work exactly the same as the ctor two above, except
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/// MachineInstr ctor - Work exactly the same as the ctor two above, except
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/// that the MachineInstr is created and added to the end of the specified
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/// that the MachineInstr is created and added to the end of the specified
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/// basic block.
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/// basic block.
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///
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MachineInstr::MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &tid)
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MachineInstr::MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &tid)
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: TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0),
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: TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0),
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MemRefs(0), MemRefsEnd(0), Parent(0) {
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MemRefs(0), MemRefsEnd(0), Parent(0) {
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