[AArch64] Removed unnecessary copy patterns with v1fx types.
- Copy patterns with float/double types are enough. - Fix typos in test case names that were using v1fx. - There is no ACLE intrinsic that uses v1f32 type. And there is no conflict of neon and non-neon ovelapped operations with this type, so there is no need to support operations with this type. - Remove v1f32 from FPR32 register and disallow v1f32 as a legal type for operations. Patch by Ana Pazos! llvm-svn: 197159
This commit is contained in:
Chad Rosier
parent
74f444cde5
commit
4055f42d22
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@ -60,7 +60,7 @@ def CC_A64_APCS : CallingConv<[
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// registers. This makes sense because the PCS does not distinguish Short
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// Vectors and Floating-point types.
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CCIfType<[v1i16, v2i8], CCBitConvertToType<f16>>,
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CCIfType<[v1i32, v4i8, v2i16, v1f32], CCBitConvertToType<f32>>,
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CCIfType<[v1i32, v4i8, v2i16], CCBitConvertToType<f32>>,
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CCIfType<[v8i8, v4i16, v2i32, v2f32, v1i64, v1f64], CCBitConvertToType<f64>>,
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CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
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CCBitConvertToType<f128>>,
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@ -64,7 +64,6 @@ AArch64TargetLowering::AArch64TargetLowering(AArch64TargetMachine &TM)
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addRegisterClass(MVT::v1i16, &AArch64::FPR16RegClass);
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addRegisterClass(MVT::v1i32, &AArch64::FPR32RegClass);
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addRegisterClass(MVT::v1i64, &AArch64::FPR64RegClass);
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addRegisterClass(MVT::v1f32, &AArch64::FPR32RegClass);
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addRegisterClass(MVT::v1f64, &AArch64::FPR64RegClass);
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addRegisterClass(MVT::v8i8, &AArch64::FPR64RegClass);
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addRegisterClass(MVT::v4i16, &AArch64::FPR64RegClass);
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@ -296,7 +295,6 @@ AArch64TargetLowering::AArch64TargetLowering(AArch64TargetMachine &TM)
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setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v1f32, Custom);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v1f64, Custom);
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@ -333,7 +331,6 @@ AArch64TargetLowering::AArch64TargetLowering(AArch64TargetMachine &TM)
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setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
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setOperationAction(ISD::SETCC, MVT::v1i64, Custom);
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setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
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setOperationAction(ISD::SETCC, MVT::v1f32, Custom);
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setOperationAction(ISD::SETCC, MVT::v2f32, Custom);
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setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
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setOperationAction(ISD::SETCC, MVT::v1f64, Custom);
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@ -5995,12 +5995,6 @@ defm : NeonI_Scalar_DUP_Copy_pattern1<DUPhv_H,
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defm : NeonI_Scalar_DUP_Copy_pattern1<DUPbv_B,
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v1i8, v16i8, i32, neon_uimm4_bare,
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v8i8, v16i8, neon_uimm3_bare>;
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defm : NeonI_Scalar_DUP_Copy_pattern1<DUPdv_D,
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v1f64, v2f64, f64, neon_uimm1_bare,
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v1f64, v2f64, neon_uimm0_bare>;
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defm : NeonI_Scalar_DUP_Copy_pattern1<DUPsv_S,
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v1f32, v4f32, f32, neon_uimm2_bare,
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v2f32, v4f32, neon_uimm1_bare>;
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defm : NeonI_Scalar_DUP_Copy_pattern2<DUPdv_D,
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v1i64, v2i64, i64, neon_uimm1_bare,
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v1i64, v2i64, neon_uimm0_bare>;
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@ -6013,12 +6007,6 @@ defm : NeonI_Scalar_DUP_Copy_pattern2<DUPhv_H,
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defm : NeonI_Scalar_DUP_Copy_pattern2<DUPbv_B,
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v1i8, v16i8, i32, neon_uimm4_bare,
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v8i8, v16i8, neon_uimm3_bare>;
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defm : NeonI_Scalar_DUP_Copy_pattern2<DUPdv_D,
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v1f64, v2f64, f64, neon_uimm1_bare,
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v1f64, v2f64, neon_uimm0_bare>;
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defm : NeonI_Scalar_DUP_Copy_pattern2<DUPsv_S,
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v1f32, v4f32, f32, neon_uimm2_bare,
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v2f32, v4f32, neon_uimm1_bare>;
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multiclass NeonI_Scalar_DUP_alias<string asmop, string asmlane,
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Instruction DUPI, Operand OpImm,
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@ -6123,7 +6111,6 @@ def : Pat<(v16i8 (bitconvert (v2f64 VPR128:$src))), (v16i8 VPR128:$src)>;
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def : Pat<(f16 (bitconvert (v1i16 FPR16:$src))), (f16 FPR16:$src)>;
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def : Pat<(f32 (bitconvert (v1i32 FPR32:$src))), (f32 FPR32:$src)>;
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def : Pat<(f64 (bitconvert (v1i64 FPR64:$src))), (f64 FPR64:$src)>;
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def : Pat<(f32 (bitconvert (v1f32 FPR32:$src))), (f32 FPR32:$src)>;
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def : Pat<(f64 (bitconvert (v1f64 FPR64:$src))), (f64 FPR64:$src)>;
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def : Pat<(i64 (bitconvert (v1i64 FPR64:$src))), (FMOVxd $src)>;
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@ -6155,7 +6142,6 @@ def : Pat<(f128 (bitconvert (v2f64 VPR128:$src))), (f128 VPR128:$src)>;
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def : Pat<(v1i16 (bitconvert (f16 FPR16:$src))), (v1i16 FPR16:$src)>;
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def : Pat<(v1i32 (bitconvert (f32 FPR32:$src))), (v1i32 FPR32:$src)>;
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def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
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def : Pat<(v1f32 (bitconvert (f32 FPR32:$src))), (v1f32 FPR32:$src)>;
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def : Pat<(v1f64 (bitconvert (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
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def : Pat<(v1i64 (bitconvert (i64 GPR64:$src))), (FMOVdx $src)>;
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@ -6688,9 +6674,6 @@ def : Pat<(i64 (vector_extract (v1i64 FPR64:$Rn), (i64 0))),
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def : Pat<(f64 (vector_extract (v1f64 FPR64:$Rn), (i64 0))),
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(f64 FPR64:$Rn)>;
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def : Pat<(f32 (vector_extract (v1f32 FPR32:$Rn), (i64 0))),
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(f32 FPR32:$Rn)>;
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def : Pat<(v1i8 (scalar_to_vector GPR32:$Rn)),
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(v1i8 (EXTRACT_SUBREG (v16i8
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(INSbw (v16i8 (IMPLICIT_DEF)), $Rn, (i64 0))),
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@ -6744,8 +6727,6 @@ def : Pat<(v2i32 (scalar_to_vector GPR32:$Rn)),
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(INSsw (v4i32 (IMPLICIT_DEF)), $Rn, (i64 0))),
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sub_64))>;
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def : Pat<(v1f32 (scalar_to_vector (f32 FPR32:$Rn))),
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(v1f32 FPR32:$Rn)>;
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def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Rn))),
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(v1f64 FPR64:$Rn)>;
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@ -7467,8 +7448,6 @@ defm SQDMULLve : NI_2VE_v3_2op<0b0, 0b1011, "sqdmull">;
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def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$src))),
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(FMOVdd $src)>;
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def : Pat<(v1f32 (scalar_to_vector (f32 FPR32:$src))),
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(FMOVss $src)>;
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// Pattern for lane in 128-bit vector
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class NI_2VEL2_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
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@ -155,7 +155,7 @@ def FPR16 : RegisterClass<"AArch64", [f16, v1i16], 16,
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(sequence "H%u", 0, 31)> {
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}
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def FPR32 : RegisterClass<"AArch64", [f32, v1i32, v1f32], 32,
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def FPR32 : RegisterClass<"AArch64", [f32, v1i32], 32,
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(sequence "S%u", 0, 31)> {
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}
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@ -20,8 +20,8 @@ define <2 x i32> @test_v8i8_to_v2i32(<8 x i8> %in) nounwind {
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ret <2 x i32> %val
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}
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define <2 x float> @test_v8i8_to_v1f32(<8 x i8> %in) nounwind{
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; CHECK: test_v8i8_to_v1f32:
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define <2 x float> @test_v8i8_to_v2f32(<8 x i8> %in) nounwind{
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; CHECK: test_v8i8_to_v2f32:
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; CHECK-NEXT: // BB#0:
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; CHECK-NEXT: ret
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@ -67,8 +67,8 @@ define <2 x i32> @test_v4i16_to_v2i32(<4 x i16> %in) nounwind {
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ret <2 x i32> %val
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}
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define <2 x float> @test_v4i16_to_v1f32(<4 x i16> %in) nounwind{
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; CHECK: test_v4i16_to_v1f32:
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define <2 x float> @test_v4i16_to_v2f32(<4 x i16> %in) nounwind{
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; CHECK: test_v4i16_to_v2f32:
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; CHECK-NEXT: // BB#0:
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; CHECK-NEXT: ret
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@ -114,8 +114,8 @@ define <2 x i32> @test_v2i32_to_v2i32(<2 x i32> %in) nounwind {
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ret <2 x i32> %val
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}
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define <2 x float> @test_v2i32_to_v1f32(<2 x i32> %in) nounwind{
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; CHECK: test_v2i32_to_v1f32:
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define <2 x float> @test_v2i32_to_v2f32(<2 x i32> %in) nounwind{
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; CHECK: test_v2i32_to_v2f32:
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; CHECK-NEXT: // BB#0:
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; CHECK-NEXT: ret
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