[Hexagon] Handle subregisters in areMemAccessesTriviallyDisjoint
llvm-svn: 308502
This commit is contained in:
parent
5abea0c97a
commit
3fce9d9c49
|
@ -1677,9 +1677,6 @@ DFAPacketizer *HexagonInstrInfo::CreateTargetScheduleState(
|
|||
// Currently AA considers the addresses in these instructions to be aliasing.
|
||||
bool HexagonInstrInfo::areMemAccessesTriviallyDisjoint(
|
||||
MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA) const {
|
||||
int OffsetA = 0, OffsetB = 0;
|
||||
unsigned SizeA = 0, SizeB = 0;
|
||||
|
||||
if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
|
||||
MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef())
|
||||
return false;
|
||||
|
@ -1689,27 +1686,47 @@ bool HexagonInstrInfo::areMemAccessesTriviallyDisjoint(
|
|||
if (MIa.mayLoad() && !isMemOp(MIa) && MIb.mayLoad() && !isMemOp(MIb))
|
||||
return true;
|
||||
|
||||
// Get base, offset, and access size in MIa.
|
||||
unsigned BaseRegA = getBaseAndOffset(MIa, OffsetA, SizeA);
|
||||
if (!BaseRegA || !SizeA)
|
||||
// Get the base register in MIa.
|
||||
unsigned BasePosA, OffsetPosA;
|
||||
if (!getBaseAndOffsetPosition(MIa, BasePosA, OffsetPosA))
|
||||
return false;
|
||||
const MachineOperand &BaseA = MIa.getOperand(BasePosA);
|
||||
unsigned BaseRegA = BaseA.getReg();
|
||||
unsigned BaseSubA = BaseA.getSubReg();
|
||||
|
||||
// Get the base register in MIb.
|
||||
unsigned BasePosB, OffsetPosB;
|
||||
if (!getBaseAndOffsetPosition(MIb, BasePosB, OffsetPosB))
|
||||
return false;
|
||||
const MachineOperand &BaseB = MIb.getOperand(BasePosB);
|
||||
unsigned BaseRegB = BaseB.getReg();
|
||||
unsigned BaseSubB = BaseB.getSubReg();
|
||||
|
||||
if (BaseRegA != BaseRegB || BaseSubA != BaseSubB)
|
||||
return false;
|
||||
|
||||
// Get base, offset, and access size in MIb.
|
||||
unsigned BaseRegB = getBaseAndOffset(MIb, OffsetB, SizeB);
|
||||
if (!BaseRegB || !SizeB)
|
||||
return false;
|
||||
// Get the access sizes.
|
||||
unsigned SizeA = (1u << (getMemAccessSize(MIa) - 1));
|
||||
unsigned SizeB = (1u << (getMemAccessSize(MIb) - 1));
|
||||
|
||||
if (BaseRegA != BaseRegB)
|
||||
// Get the offsets. Handle immediates only for now.
|
||||
const MachineOperand &OffA = MIa.getOperand(OffsetPosA);
|
||||
const MachineOperand &OffB = MIb.getOperand(OffsetPosB);
|
||||
if (!MIa.getOperand(OffsetPosA).isImm() ||
|
||||
!MIb.getOperand(OffsetPosB).isImm())
|
||||
return false;
|
||||
int OffsetA = OffA.getImm();
|
||||
int OffsetB = OffB.getImm();
|
||||
|
||||
// This is a mem access with the same base register and known offsets from it.
|
||||
// Reason about it.
|
||||
if (OffsetA > OffsetB) {
|
||||
uint64_t offDiff = (uint64_t)((int64_t)OffsetA - (int64_t)OffsetB);
|
||||
return (SizeB <= offDiff);
|
||||
} else if (OffsetA < OffsetB) {
|
||||
uint64_t offDiff = (uint64_t)((int64_t)OffsetB - (int64_t)OffsetA);
|
||||
return (SizeA <= offDiff);
|
||||
uint64_t OffDiff = (uint64_t)((int64_t)OffsetA - (int64_t)OffsetB);
|
||||
return SizeB <= OffDiff;
|
||||
}
|
||||
if (OffsetA < OffsetB) {
|
||||
uint64_t OffDiff = (uint64_t)((int64_t)OffsetB - (int64_t)OffsetA);
|
||||
return SizeA <= OffDiff;
|
||||
}
|
||||
|
||||
return false;
|
||||
|
|
Loading…
Reference in New Issue