R600/SI: Add preliminary support for flat address space
llvm-svn: 217777
This commit is contained in:
Matt Arsenault
parent
65f67e4dfe
commit
3f98140c87
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@ -81,6 +81,11 @@ def FeatureCFALUBug : SubtargetFeature<"cfalubug",
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"true",
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"GPU has CF_ALU bug">;
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def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
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"FlatAddressSpace",
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"true",
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"Support flat address space">;
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class SubtargetFeatureFetchLimit <string Value> :
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SubtargetFeature <"fetch"#Value,
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"TexVTXClauseSize",
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@ -135,7 +140,7 @@ def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
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def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
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[Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
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FeatureWavefrontSize64]>;
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FeatureWavefrontSize64, FeatureFlatAddressSpace]>;
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//===----------------------------------------------------------------------===//
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def AMDGPUInstrInfo : InstrInfo {
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@ -240,6 +240,7 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
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unsigned MaxSGPR = 0;
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unsigned MaxVGPR = 0;
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bool VCCUsed = false;
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bool FlatUsed = false;
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const SIRegisterInfo *RI = static_cast<const SIRegisterInfo *>(
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TM.getSubtargetImpl()->getRegisterInfo());
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@ -262,6 +263,11 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
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reg == AMDGPU::VCC_HI) {
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VCCUsed = true;
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continue;
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} else if (reg == AMDGPU::FLAT_SCR ||
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reg == AMDGPU::FLAT_SCR_LO ||
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reg == AMDGPU::FLAT_SCR_HI) {
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FlatUsed = true;
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continue;
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}
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switch (reg) {
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@ -322,6 +328,9 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
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if (VCCUsed)
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MaxSGPR += 2;
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if (FlatUsed)
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MaxSGPR += 2;
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// We found the maximum register index. They start at 0, so add one to get the
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// number of registers.
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ProgInfo.NumVGPR = MaxVGPR + 1;
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@ -340,6 +349,8 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
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const MachineFrameInfo *FrameInfo = MF.getFrameInfo();
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ProgInfo.ScratchSize = FrameInfo->estimateStackSize(MF);
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ProgInfo.FlatUsed = FlatUsed;
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ProgInfo.VCCUsed = VCCUsed;
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ProgInfo.CodeLen = CodeSize;
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}
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@ -402,6 +413,9 @@ void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
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OutStreamer.EmitIntValue(R_00B860_COMPUTE_TMPRING_SIZE, 4);
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OutStreamer.EmitIntValue(S_00B860_WAVESIZE(ScratchBlocks), 4);
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// TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
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// 0" comment but I don't see a corresponding field in the register spec.
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} else {
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OutStreamer.EmitIntValue(RsrcReg, 4);
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OutStreamer.EmitIntValue(S_00B028_VGPRS(KernelInfo.NumVGPR / 4) |
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@ -33,6 +33,8 @@ private:
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DebugMode(0),
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IEEEMode(0),
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ScratchSize(0),
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FlatUsed(false),
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VCCUsed(false),
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CodeLen(0) {}
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// Fields set in PGM_RSRC1 pm4 packet.
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@ -46,7 +48,10 @@ private:
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uint32_t IEEEMode;
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uint32_t ScratchSize;
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bool FlatUsed;
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// Bonus information for debugging.
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bool VCCUsed;
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uint64_t CodeLen;
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};
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@ -65,6 +65,7 @@ private:
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static bool checkPrivateAddress(const MachineMemOperand *Op);
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static bool isGlobalStore(const StoreSDNode *N);
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static bool isFlatStore(const StoreSDNode *N);
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static bool isPrivateStore(const StoreSDNode *N);
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static bool isLocalStore(const StoreSDNode *N);
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static bool isRegionStore(const StoreSDNode *N);
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@ -72,6 +73,7 @@ private:
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bool isCPLoad(const LoadSDNode *N) const;
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bool isConstantLoad(const LoadSDNode *N, int cbID) const;
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bool isGlobalLoad(const LoadSDNode *N) const;
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bool isFlatLoad(const LoadSDNode *N) const;
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bool isParamLoad(const LoadSDNode *N) const;
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bool isPrivateLoad(const LoadSDNode *N) const;
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bool isLocalLoad(const LoadSDNode *N) const;
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@ -104,6 +106,7 @@ private:
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bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &SOffset,
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SDValue &Offset, SDValue &GLC, SDValue &SLC,
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SDValue &TFE) const;
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SDNode *SelectAddrSpaceCast(SDNode *N);
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bool SelectVOP3Mods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
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bool SelectVOP3Mods0(SDValue In, SDValue &Src, SDValue &SrcMods,
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SDValue &Clamp, SDValue &Omod) const;
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@ -484,6 +487,8 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
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case AMDGPUISD::DIV_SCALE: {
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return SelectDIV_SCALE(N);
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}
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case ISD::ADDRSPACECAST:
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return SelectAddrSpaceCast(N);
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}
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return SelectCode(N);
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}
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@ -522,6 +527,10 @@ bool AMDGPUDAGToDAGISel::isLocalStore(const StoreSDNode *N) {
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return checkType(N->getMemOperand()->getValue(), AMDGPUAS::LOCAL_ADDRESS);
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}
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bool AMDGPUDAGToDAGISel::isFlatStore(const StoreSDNode *N) {
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return checkType(N->getMemOperand()->getValue(), AMDGPUAS::FLAT_ADDRESS);
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}
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bool AMDGPUDAGToDAGISel::isRegionStore(const StoreSDNode *N) {
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return checkType(N->getMemOperand()->getValue(), AMDGPUAS::REGION_ADDRESS);
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}
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@ -553,6 +562,10 @@ bool AMDGPUDAGToDAGISel::isLocalLoad(const LoadSDNode *N) const {
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return checkType(N->getMemOperand()->getValue(), AMDGPUAS::LOCAL_ADDRESS);
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}
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bool AMDGPUDAGToDAGISel::isFlatLoad(const LoadSDNode *N) const {
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return checkType(N->getMemOperand()->getValue(), AMDGPUAS::FLAT_ADDRESS);
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}
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bool AMDGPUDAGToDAGISel::isRegionLoad(const LoadSDNode *N) const {
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return checkType(N->getMemOperand()->getValue(), AMDGPUAS::REGION_ADDRESS);
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}
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@ -582,10 +595,11 @@ bool AMDGPUDAGToDAGISel::isPrivateLoad(const LoadSDNode *N) const {
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const Value *MemVal = N->getMemOperand()->getValue();
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if (!checkType(MemVal, AMDGPUAS::LOCAL_ADDRESS) &&
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!checkType(MemVal, AMDGPUAS::GLOBAL_ADDRESS) &&
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!checkType(MemVal, AMDGPUAS::FLAT_ADDRESS) &&
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!checkType(MemVal, AMDGPUAS::REGION_ADDRESS) &&
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!checkType(MemVal, AMDGPUAS::CONSTANT_ADDRESS) &&
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!checkType(MemVal, AMDGPUAS::PARAM_D_ADDRESS) &&
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!checkType(MemVal, AMDGPUAS::PARAM_I_ADDRESS)){
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!checkType(MemVal, AMDGPUAS::PARAM_I_ADDRESS)) {
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return true;
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}
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return false;
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@ -1005,6 +1019,66 @@ bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
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return false;
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}
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// FIXME: This is incorrect and only enough to be able to compile.
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SDNode *AMDGPUDAGToDAGISel::SelectAddrSpaceCast(SDNode *N) {
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AddrSpaceCastSDNode *ASC = cast<AddrSpaceCastSDNode>(N);
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SDLoc DL(N);
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assert(Subtarget.hasFlatAddressSpace() &&
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"addrspacecast only supported with flat address space!");
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assert((ASC->getSrcAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS &&
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ASC->getDestAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS) &&
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"Cannot cast address space to / from constant address!");
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assert((ASC->getSrcAddressSpace() == AMDGPUAS::FLAT_ADDRESS ||
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ASC->getDestAddressSpace() == AMDGPUAS::FLAT_ADDRESS) &&
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"Can only cast to / from flat address space!");
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// The flat instructions read the address as the index of the VGPR holding the
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// address, so casting should just be reinterpreting the base VGPR, so just
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// insert trunc / bitcast / zext.
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SDValue Src = ASC->getOperand(0);
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EVT DestVT = ASC->getValueType(0);
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EVT SrcVT = Src.getValueType();
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unsigned SrcSize = SrcVT.getSizeInBits();
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unsigned DestSize = DestVT.getSizeInBits();
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if (SrcSize > DestSize) {
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assert(SrcSize == 64 && DestSize == 32);
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return CurDAG->getMachineNode(
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TargetOpcode::EXTRACT_SUBREG,
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DL,
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DestVT,
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Src,
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CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32));
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}
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if (DestSize > SrcSize) {
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assert(SrcSize == 32 && DestSize == 64);
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SDValue RC = CurDAG->getTargetConstant(AMDGPU::VSrc_64RegClassID, MVT::i32);
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const SDValue Ops[] = {
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RC,
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Src,
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CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32),
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SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, SDLoc(N), MVT::i32,
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CurDAG->getConstant(0, MVT::i32)), 0),
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CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32)
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};
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return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE,
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SDLoc(N), N->getValueType(0), Ops);
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}
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assert(SrcSize == 64 && DestSize == 64);
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return CurDAG->getNode(ISD::BITCAST, DL, DestVT, Src).getNode();
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}
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bool AMDGPUDAGToDAGISel::SelectVOP3Mods(SDValue In, SDValue &Src,
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SDValue &SrcMods) const {
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@ -95,6 +95,7 @@ protected:
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MachineInstr *MI,
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const SmallVectorImpl<unsigned> &Ops,
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MachineInstr *LoadMI) const override;
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public:
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/// \returns the smallest register index that will be accessed by an indirect
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/// read or write or -1 if indirect addressing is not used by this program.
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int getIndirectIndexBegin(const MachineFunction &MF) const;
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@ -103,7 +104,6 @@ protected:
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/// read or write or -1 if indirect addressing is not used by this program.
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int getIndirectIndexEnd(const MachineFunction &MF) const;
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public:
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bool canFoldMemoryOperand(const MachineInstr *MI,
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const SmallVectorImpl<unsigned> &Ops) const override;
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bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
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@ -195,6 +195,14 @@ def sextloadi8_global : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{
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return isGlobalLoad(dyn_cast<LoadSDNode>(N));
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}]>;
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def az_extloadi8_flat : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{
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return isFlatLoad(dyn_cast<LoadSDNode>(N));
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}]>;
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def sextloadi8_flat : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{
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return isFlatLoad(dyn_cast<LoadSDNode>(N));
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}]>;
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def az_extloadi8_constant : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{
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return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
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}]>;
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@ -223,6 +231,14 @@ def sextloadi16_global : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{
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return isGlobalLoad(dyn_cast<LoadSDNode>(N));
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}]>;
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def az_extloadi16_flat : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{
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return isFlatLoad(dyn_cast<LoadSDNode>(N));
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}]>;
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def sextloadi16_flat : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{
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return isFlatLoad(dyn_cast<LoadSDNode>(N));
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}]>;
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def az_extloadi16_constant : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{
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return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
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}]>;
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@ -248,6 +264,11 @@ def az_extloadi32_global : PatFrag<(ops node:$ptr),
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return isGlobalLoad(dyn_cast<LoadSDNode>(N));
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}]>;
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def az_extloadi32_flat : PatFrag<(ops node:$ptr),
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(az_extloadi32 node:$ptr), [{
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return isFlatLoad(dyn_cast<LoadSDNode>(N));
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}]>;
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def az_extloadi32_constant : PatFrag<(ops node:$ptr),
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(az_extloadi32 node:$ptr), [{
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return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
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@ -263,6 +284,16 @@ def truncstorei16_global : PatFrag<(ops node:$val, node:$ptr),
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return isGlobalStore(dyn_cast<StoreSDNode>(N));
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}]>;
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def truncstorei8_flat : PatFrag<(ops node:$val, node:$ptr),
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(truncstorei8 node:$val, node:$ptr), [{
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return isFlatStore(dyn_cast<StoreSDNode>(N));
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}]>;
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def truncstorei16_flat : PatFrag<(ops node:$val, node:$ptr),
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(truncstorei16 node:$val, node:$ptr), [{
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return isFlatStore(dyn_cast<StoreSDNode>(N));
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}]>;
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def local_store : PatFrag<(ops node:$val, node:$ptr),
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(store node:$val, node:$ptr), [{
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return isLocalStore(dyn_cast<StoreSDNode>(N));
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@ -318,6 +349,7 @@ def mskor_global : PatFrag<(ops node:$val, node:$ptr),
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return dyn_cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS;
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}]>;
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def atomic_cmp_swap_32_local :
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PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
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(atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
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@ -334,6 +366,20 @@ def atomic_cmp_swap_64_local :
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AN->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
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}]>;
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def flat_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
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return isFlatLoad(dyn_cast<LoadSDNode>(N));
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}]>;
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def flat_store : PatFrag<(ops node:$val, node:$ptr),
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(store node:$val, node:$ptr), [{
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return isFlatStore(dyn_cast<StoreSDNode>(N));
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}]>;
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def mskor_flat : PatFrag<(ops node:$val, node:$ptr),
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(AMDGPUstore_mskor node:$val, node:$ptr), [{
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return dyn_cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::FLAT_ADDRESS;
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}]>;
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//===----------------------------------------------------------------------===//
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// Misc Pattern Fragments
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//===----------------------------------------------------------------------===//
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@ -12,7 +12,9 @@ void AMDGPUMachineFunction::anchor() {}
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AMDGPUMachineFunction::AMDGPUMachineFunction(const MachineFunction &MF) :
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MachineFunctionInfo(),
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ShaderType(ShaderType::COMPUTE),
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LDSSize(0) {
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LDSSize(0),
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ScratchSize(0),
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IsKernel(true) {
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AttributeSet Set = MF.getFunction()->getAttributes();
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Attribute A = Set.getAttribute(AttributeSet::FunctionIndex,
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ShaderTypeAttribute);
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@ -33,6 +33,9 @@ public:
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unsigned getShaderType() const {
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return ShaderType;
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}
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unsigned ScratchSize;
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bool IsKernel;
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};
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}
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@ -77,14 +77,14 @@ AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef GPU, StringRef FS,
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DumpCode(false), R600ALUInst(false), HasVertexCache(false),
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TexVTXClauseSize(0), Gen(AMDGPUSubtarget::R600), FP64(false),
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FP64Denormals(false), FP32Denormals(false), CaymanISA(false),
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EnableIRStructurizer(true), EnablePromoteAlloca(false), EnableIfCvt(true),
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FlatAddressSpace(false), EnableIRStructurizer(true),
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EnablePromoteAlloca(false), EnableIfCvt(true),
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WavefrontSize(0), CFALUBug(false), LocalMemorySize(0),
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DL(computeDataLayout(initializeSubtargetDependencies(GPU, FS))),
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FrameLowering(TargetFrameLowering::StackGrowsUp,
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64 * 16, // Maximum stack alignment (long16)
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0),
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InstrItins(getInstrItineraryForCPU(GPU)) {
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if (getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
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InstrInfo.reset(new R600InstrInfo(*this));
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TLInfo.reset(new R600TargetLowering(TM));
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@ -56,6 +56,7 @@ private:
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bool FP64Denormals;
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bool FP32Denormals;
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bool CaymanISA;
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bool FlatAddressSpace;
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bool EnableIRStructurizer;
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bool EnablePromoteAlloca;
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bool EnableIfCvt;
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@ -124,6 +125,10 @@ public:
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return FP64Denormals;
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}
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bool hasFlatAddressSpace() const {
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return FlatAddressSpace;
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}
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bool hasBFE() const {
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return (getGeneration() >= EVERGREEN);
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}
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@ -98,6 +98,27 @@ void AMDGPUInstPrinter::printRegOperand(unsigned reg, raw_ostream &O) {
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case AMDGPU::M0:
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O << "m0";
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return;
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case AMDGPU::FLAT_SCR:
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O << "flat_scratch";
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return;
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case AMDGPU::VCC_LO:
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O << "vcc_lo";
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return;
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case AMDGPU::VCC_HI:
|
||||
O << "vcc_hi";
|
||||
return;
|
||||
case AMDGPU::EXEC_LO:
|
||||
O << "exec_lo";
|
||||
return;
|
||||
case AMDGPU::EXEC_HI:
|
||||
O << "exec_hi";
|
||||
return;
|
||||
case AMDGPU::FLAT_SCR_LO:
|
||||
O << "flat_scratch_lo";
|
||||
return;
|
||||
case AMDGPU::FLAT_SCR_HI:
|
||||
O << "flat_scratch_hi";
|
||||
return;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -22,7 +22,8 @@ enum {
|
|||
VOPC = 1 << 8,
|
||||
SALU = 1 << 9,
|
||||
MUBUF = 1 << 10,
|
||||
MTBUF = 1 << 11
|
||||
MTBUF = 1 << 11,
|
||||
FLAT = 1 << 12
|
||||
};
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -26,6 +26,7 @@ class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
|
|||
field bits<1> SALU = 0;
|
||||
field bits<1> MUBUF = 0;
|
||||
field bits<1> MTBUF = 0;
|
||||
field bits<1> FLAT = 0;
|
||||
|
||||
// These need to be kept in sync with the enum in SIInstrFlags.
|
||||
let TSFlags{0} = VM_CNT;
|
||||
|
|
@ -40,6 +41,7 @@ class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
|
|||
let TSFlags{9} = SALU;
|
||||
let TSFlags{10} = MUBUF;
|
||||
let TSFlags{11} = MTBUF;
|
||||
let TSFlags{12} = FLAT;
|
||||
}
|
||||
|
||||
class Enc32 {
|
||||
|
|
@ -425,8 +427,27 @@ class MIMGe <bits<7> op> : Enc64 {
|
|||
let Inst{57-53} = SSAMP{6-2};
|
||||
}
|
||||
|
||||
class EXPe : Enc64 {
|
||||
class FLATe<bits<7> op> : Enc64 {
|
||||
bits<8> addr;
|
||||
bits<8> data;
|
||||
bits<8> vdst;
|
||||
bits<1> slc;
|
||||
bits<1> glc;
|
||||
bits<1> tfe;
|
||||
|
||||
// 15-0 is reserved.
|
||||
let Inst{16} = glc;
|
||||
let Inst{17} = slc;
|
||||
let Inst{24-18} = op;
|
||||
let Inst{31-26} = 0x37; // Encoding.
|
||||
let Inst{39-32} = addr;
|
||||
let Inst{47-40} = data;
|
||||
// 54-48 is reserved.
|
||||
let Inst{55} = tfe;
|
||||
let Inst{63-56} = vdst;
|
||||
}
|
||||
|
||||
class EXPe : Enc64 {
|
||||
bits<4> EN;
|
||||
bits<6> TGT;
|
||||
bits<1> COMPR;
|
||||
|
|
@ -533,6 +554,21 @@ class MTBUF <bits<3> op, dag outs, dag ins, string asm, list<dag> pattern> :
|
|||
let UseNamedOperandTable = 1;
|
||||
}
|
||||
|
||||
class FLAT <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
|
||||
InstSI<outs, ins, asm, pattern>, FLATe <op> {
|
||||
let FLAT = 1;
|
||||
// Internally, FLAT instruction are executed as both an LDS and a
|
||||
// Buffer instruction; so, they increment both VM_CNT and LGKM_CNT
|
||||
// and are not considered done until both have been decremented.
|
||||
let VM_CNT = 1;
|
||||
let LGKM_CNT = 1;
|
||||
|
||||
let Uses = [EXEC, FLAT_SCR]; // M0
|
||||
|
||||
let UseNamedOperandTable = 1;
|
||||
let hasSideEffects = 0;
|
||||
}
|
||||
|
||||
class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
|
||||
InstSI <outs, ins, asm, pattern>, MIMGe <op> {
|
||||
|
||||
|
|
|
|||
|
|
@ -638,6 +638,10 @@ bool SIInstrInfo::isMTBUF(uint16_t Opcode) const {
|
|||
return get(Opcode).TSFlags & SIInstrFlags::MTBUF;
|
||||
}
|
||||
|
||||
bool SIInstrInfo::isFLAT(uint16_t Opcode) const {
|
||||
return get(Opcode).TSFlags & SIInstrFlags::FLAT;
|
||||
}
|
||||
|
||||
bool SIInstrInfo::isVOP1(uint16_t Opcode) const {
|
||||
return get(Opcode).TSFlags & SIInstrFlags::VOP1;
|
||||
}
|
||||
|
|
@ -843,6 +847,10 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
|
|||
if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC)
|
||||
++ConstantBusCount;
|
||||
|
||||
// FLAT_SCR is just an SGPR pair.
|
||||
if (!MO.isImplicit() && (MO.getReg() == AMDGPU::FLAT_SCR))
|
||||
++ConstantBusCount;
|
||||
|
||||
// SGPRs use the constant bus
|
||||
if (MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC ||
|
||||
(!MO.isImplicit() &&
|
||||
|
|
|
|||
|
|
@ -108,6 +108,7 @@ public:
|
|||
bool isSMRD(uint16_t Opcode) const;
|
||||
bool isMUBUF(uint16_t Opcode) const;
|
||||
bool isMTBUF(uint16_t Opcode) const;
|
||||
bool isFLAT(uint16_t Opcode) const;
|
||||
bool isVOP1(uint16_t Opcode) const;
|
||||
bool isVOP2(uint16_t Opcode) const;
|
||||
bool isVOP3(uint16_t Opcode) const;
|
||||
|
|
|
|||
|
|
@ -209,6 +209,7 @@ def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
|
|||
def SIOperand {
|
||||
int ZERO = 0x80;
|
||||
int VCC = 0x6A;
|
||||
int FLAT_SCR = 0x68;
|
||||
}
|
||||
|
||||
def SRCMODS {
|
||||
|
|
@ -1063,6 +1064,30 @@ multiclass MUBUF_Store_Helper <bits<7> op, string name, RegisterClass vdataClass
|
|||
}
|
||||
}
|
||||
|
||||
class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
|
||||
FLAT <op, (outs regClass:$data),
|
||||
(ins VReg_64:$addr),
|
||||
asm#" $data, $addr, [M0, FLAT_SCRATCH]", []> {
|
||||
let glc = 0;
|
||||
let slc = 0;
|
||||
let tfe = 0;
|
||||
let mayLoad = 1;
|
||||
}
|
||||
|
||||
class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
|
||||
FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr),
|
||||
name#" $data, $addr, [M0, FLAT_SCRATCH]",
|
||||
[]> {
|
||||
|
||||
let mayLoad = 0;
|
||||
let mayStore = 1;
|
||||
|
||||
// Encoding
|
||||
let glc = 0;
|
||||
let slc = 0;
|
||||
let tfe = 0;
|
||||
}
|
||||
|
||||
class MTBUF_Load_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
|
||||
op,
|
||||
(outs regClass:$dst),
|
||||
|
|
|
|||
|
|
@ -31,6 +31,7 @@ def isSI : Predicate<"Subtarget.getGeneration() "
|
|||
|
||||
def isCI : Predicate<"Subtarget.getGeneration() "
|
||||
">= AMDGPUSubtarget::SEA_ISLANDS">;
|
||||
def HasFlatAddressSpace : Predicate<"Subtarget.hasFlatAddressSpace()">;
|
||||
|
||||
def isCFDepth0 : Predicate<"isCFDepth0()">;
|
||||
|
||||
|
|
@ -1043,6 +1044,80 @@ defm IMAGE_SAMPLE_C_CD_CL_O : MIMG_Sampler <0x0000006f, "IMAGE_SAMPLE_C_CD_CL_O"
|
|||
//def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"IMAGE_RSRC256", 0x0000007e>;
|
||||
//def IMAGE_SAMPLER : MIMG_NoPattern_ <"IMAGE_SAMPLER", 0x0000007f>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Flat Instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
let Predicates = [HasFlatAddressSpace] in {
|
||||
def FLAT_LOAD_UBYTE : FLAT_Load_Helper <0x00000008, "FLAT_LOAD_UBYTE", VReg_32>;
|
||||
def FLAT_LOAD_SBYTE : FLAT_Load_Helper <0x00000009, "FLAT_LOAD_SBYTE", VReg_32>;
|
||||
def FLAT_LOAD_USHORT : FLAT_Load_Helper <0x0000000a, "FLAT_LOAD_USHORT", VReg_32>;
|
||||
def FLAT_LOAD_SSHORT : FLAT_Load_Helper <0x0000000b, "FLAT_LOAD_SSHORT", VReg_32>;
|
||||
def FLAT_LOAD_DWORD : FLAT_Load_Helper <0x0000000c, "FLAT_LOAD_DWORD", VReg_32>;
|
||||
def FLAT_LOAD_DWORDX2 : FLAT_Load_Helper <0x0000000d, "FLAT_LOAD_DWORDX2", VReg_64>;
|
||||
def FLAT_LOAD_DWORDX4 : FLAT_Load_Helper <0x0000000e, "FLAT_LOAD_DWORDX4", VReg_128>;
|
||||
def FLAT_LOAD_DWORDX3 : FLAT_Load_Helper <0x00000010, "FLAT_LOAD_DWORDX3", VReg_96>;
|
||||
|
||||
def FLAT_STORE_BYTE : FLAT_Store_Helper <
|
||||
0x00000018, "FLAT_STORE_BYTE", VReg_32
|
||||
>;
|
||||
|
||||
def FLAT_STORE_SHORT : FLAT_Store_Helper <
|
||||
0x0000001a, "FLAT_STORE_SHORT", VReg_32
|
||||
>;
|
||||
|
||||
def FLAT_STORE_DWORD : FLAT_Store_Helper <
|
||||
0x0000001c, "FLAT_STORE_DWORD", VReg_32
|
||||
>;
|
||||
|
||||
def FLAT_STORE_DWORDX2 : FLAT_Store_Helper <
|
||||
0x0000001d, "FLAT_STORE_DWORDX2", VReg_64
|
||||
>;
|
||||
|
||||
def FLAT_STORE_DWORDX4 : FLAT_Store_Helper <
|
||||
0x0000001e, "FLAT_STORE_DWORDX4", VReg_128
|
||||
>;
|
||||
|
||||
def FLAT_STORE_DWORDX3 : FLAT_Store_Helper <
|
||||
0x0000001e, "FLAT_STORE_DWORDX3", VReg_96
|
||||
>;
|
||||
|
||||
//def FLAT_ATOMIC_SWAP : FLAT_ <0x00000030, "FLAT_ATOMIC_SWAP", []>;
|
||||
//def FLAT_ATOMIC_CMPSWAP : FLAT_ <0x00000031, "FLAT_ATOMIC_CMPSWAP", []>;
|
||||
//def FLAT_ATOMIC_ADD : FLAT_ <0x00000032, "FLAT_ATOMIC_ADD", []>;
|
||||
//def FLAT_ATOMIC_SUB : FLAT_ <0x00000033, "FLAT_ATOMIC_SUB", []>;
|
||||
//def FLAT_ATOMIC_RSUB : FLAT_ <0x00000034, "FLAT_ATOMIC_RSUB", []>;
|
||||
//def FLAT_ATOMIC_SMIN : FLAT_ <0x00000035, "FLAT_ATOMIC_SMIN", []>;
|
||||
//def FLAT_ATOMIC_UMIN : FLAT_ <0x00000036, "FLAT_ATOMIC_UMIN", []>;
|
||||
//def FLAT_ATOMIC_SMAX : FLAT_ <0x00000037, "FLAT_ATOMIC_SMAX", []>;
|
||||
//def FLAT_ATOMIC_UMAX : FLAT_ <0x00000038, "FLAT_ATOMIC_UMAX", []>;
|
||||
//def FLAT_ATOMIC_AND : FLAT_ <0x00000039, "FLAT_ATOMIC_AND", []>;
|
||||
//def FLAT_ATOMIC_OR : FLAT_ <0x0000003a, "FLAT_ATOMIC_OR", []>;
|
||||
//def FLAT_ATOMIC_XOR : FLAT_ <0x0000003b, "FLAT_ATOMIC_XOR", []>;
|
||||
//def FLAT_ATOMIC_INC : FLAT_ <0x0000003c, "FLAT_ATOMIC_INC", []>;
|
||||
//def FLAT_ATOMIC_DEC : FLAT_ <0x0000003d, "FLAT_ATOMIC_DEC", []>;
|
||||
//def FLAT_ATOMIC_FCMPSWAP : FLAT_ <0x0000003e, "FLAT_ATOMIC_FCMPSWAP", []>;
|
||||
//def FLAT_ATOMIC_FMIN : FLAT_ <0x0000003f, "FLAT_ATOMIC_FMIN", []>;
|
||||
//def FLAT_ATOMIC_FMAX : FLAT_ <0x00000040, "FLAT_ATOMIC_FMAX", []>;
|
||||
//def FLAT_ATOMIC_SWAP_X2 : FLAT_X2 <0x00000050, "FLAT_ATOMIC_SWAP_X2", []>;
|
||||
//def FLAT_ATOMIC_CMPSWAP_X2 : FLAT_X2 <0x00000051, "FLAT_ATOMIC_CMPSWAP_X2", []>;
|
||||
//def FLAT_ATOMIC_ADD_X2 : FLAT_X2 <0x00000052, "FLAT_ATOMIC_ADD_X2", []>;
|
||||
//def FLAT_ATOMIC_SUB_X2 : FLAT_X2 <0x00000053, "FLAT_ATOMIC_SUB_X2", []>;
|
||||
//def FLAT_ATOMIC_RSUB_X2 : FLAT_X2 <0x00000054, "FLAT_ATOMIC_RSUB_X2", []>;
|
||||
//def FLAT_ATOMIC_SMIN_X2 : FLAT_X2 <0x00000055, "FLAT_ATOMIC_SMIN_X2", []>;
|
||||
//def FLAT_ATOMIC_UMIN_X2 : FLAT_X2 <0x00000056, "FLAT_ATOMIC_UMIN_X2", []>;
|
||||
//def FLAT_ATOMIC_SMAX_X2 : FLAT_X2 <0x00000057, "FLAT_ATOMIC_SMAX_X2", []>;
|
||||
//def FLAT_ATOMIC_UMAX_X2 : FLAT_X2 <0x00000058, "FLAT_ATOMIC_UMAX_X2", []>;
|
||||
//def FLAT_ATOMIC_AND_X2 : FLAT_X2 <0x00000059, "FLAT_ATOMIC_AND_X2", []>;
|
||||
//def FLAT_ATOMIC_OR_X2 : FLAT_X2 <0x0000005a, "FLAT_ATOMIC_OR_X2", []>;
|
||||
//def FLAT_ATOMIC_XOR_X2 : FLAT_X2 <0x0000005b, "FLAT_ATOMIC_XOR_X2", []>;
|
||||
//def FLAT_ATOMIC_INC_X2 : FLAT_X2 <0x0000005c, "FLAT_ATOMIC_INC_X2", []>;
|
||||
//def FLAT_ATOMIC_DEC_X2 : FLAT_X2 <0x0000005d, "FLAT_ATOMIC_DEC_X2", []>;
|
||||
//def FLAT_ATOMIC_FCMPSWAP_X2 : FLAT_X2 <0x0000005e, "FLAT_ATOMIC_FCMPSWAP_X2", []>;
|
||||
//def FLAT_ATOMIC_FMIN_X2 : FLAT_X2 <0x0000005f, "FLAT_ATOMIC_FMIN_X2", []>;
|
||||
//def FLAT_ATOMIC_FMAX_X2 : FLAT_X2 <0x00000060, "FLAT_ATOMIC_FMAX_X2", []>;
|
||||
|
||||
} // End HasFlatAddressSpace predicate
|
||||
//===----------------------------------------------------------------------===//
|
||||
// VOP1 Instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
|
@ -2822,6 +2897,37 @@ defm V_MAD_I64_I32 : VOP3Inst <0x00000177, "V_MAD_I64_I32",
|
|||
|
||||
} // End iSCI
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Flat Patterns
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
class FLATLoad_Pattern <FLAT Instr_ADDR64, ValueType vt,
|
||||
PatFrag flat_ld> :
|
||||
Pat <(vt (flat_ld i64:$ptr)),
|
||||
(Instr_ADDR64 $ptr)
|
||||
>;
|
||||
|
||||
def : FLATLoad_Pattern <FLAT_LOAD_SBYTE, i32, sextloadi8_flat>;
|
||||
def : FLATLoad_Pattern <FLAT_LOAD_UBYTE, i32, az_extloadi8_flat>;
|
||||
def : FLATLoad_Pattern <FLAT_LOAD_SSHORT, i32, sextloadi16_flat>;
|
||||
def : FLATLoad_Pattern <FLAT_LOAD_USHORT, i32, az_extloadi16_flat>;
|
||||
def : FLATLoad_Pattern <FLAT_LOAD_DWORD, i32, flat_load>;
|
||||
def : FLATLoad_Pattern <FLAT_LOAD_DWORDX2, i64, flat_load>;
|
||||
def : FLATLoad_Pattern <FLAT_LOAD_DWORDX2, i64, az_extloadi32_flat>;
|
||||
def : FLATLoad_Pattern <FLAT_LOAD_DWORDX2, v2i32, flat_load>;
|
||||
def : FLATLoad_Pattern <FLAT_LOAD_DWORDX4, v4i32, flat_load>;
|
||||
|
||||
class FLATStore_Pattern <FLAT Instr, ValueType vt, PatFrag st> :
|
||||
Pat <(st vt:$value, i64:$ptr),
|
||||
(Instr $value, $ptr)
|
||||
>;
|
||||
|
||||
def : FLATStore_Pattern <FLAT_STORE_BYTE, i32, truncstorei8_flat>;
|
||||
def : FLATStore_Pattern <FLAT_STORE_SHORT, i32, truncstorei16_flat>;
|
||||
def : FLATStore_Pattern <FLAT_STORE_DWORD, i32, flat_store>;
|
||||
def : FLATStore_Pattern <FLAT_STORE_DWORDX2, i64, flat_store>;
|
||||
def : FLATStore_Pattern <FLAT_STORE_DWORDX2, v2i32, flat_store>;
|
||||
def : FLATStore_Pattern <FLAT_STORE_DWORDX4, v4i32, flat_store>;
|
||||
|
||||
/********** ====================== **********/
|
||||
/********** Indirect adressing **********/
|
||||
|
|
|
|||
|
|
@ -52,6 +52,7 @@
|
|||
#include "AMDGPUSubtarget.h"
|
||||
#include "SIInstrInfo.h"
|
||||
#include "SIMachineFunctionInfo.h"
|
||||
#include "llvm/CodeGen/MachineFrameInfo.h"
|
||||
#include "llvm/CodeGen/MachineFunction.h"
|
||||
#include "llvm/CodeGen/MachineFunctionPass.h"
|
||||
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
||||
|
|
@ -451,6 +452,7 @@ bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) {
|
|||
bool HaveKill = false;
|
||||
bool NeedM0 = false;
|
||||
bool NeedWQM = false;
|
||||
bool NeedFlat = false;
|
||||
unsigned Depth = 0;
|
||||
|
||||
for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
|
||||
|
|
@ -467,6 +469,12 @@ bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) {
|
|||
NeedWQM = true;
|
||||
}
|
||||
|
||||
// Flat uses m0 in case it needs to access LDS.
|
||||
if (TII->isFLAT(MI.getOpcode())) {
|
||||
NeedM0 = true;
|
||||
NeedFlat = true;
|
||||
}
|
||||
|
||||
switch (MI.getOpcode()) {
|
||||
default: break;
|
||||
case AMDGPU::SI_IF:
|
||||
|
|
@ -532,7 +540,6 @@ bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) {
|
|||
case AMDGPU::V_INTERP_MOV_F32:
|
||||
NeedWQM = true;
|
||||
break;
|
||||
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -550,5 +557,42 @@ bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) {
|
|||
AMDGPU::EXEC).addReg(AMDGPU::EXEC);
|
||||
}
|
||||
|
||||
// FIXME: This seems inappropriate to do here.
|
||||
if (NeedFlat && MFI->IsKernel) {
|
||||
// Insert the prologue initializing the SGPRs pointing to the scratch space
|
||||
// for flat accesses.
|
||||
const MachineFrameInfo *FrameInfo = MF.getFrameInfo();
|
||||
|
||||
// TODO: What to use with function calls?
|
||||
|
||||
// FIXME: This is reporting stack size that is used in a scratch buffer
|
||||
// rather than registers as well.
|
||||
uint64_t StackSizeBytes = FrameInfo->getStackSize();
|
||||
|
||||
int IndirectBegin
|
||||
= static_cast<const AMDGPUInstrInfo*>(TII)->getIndirectIndexBegin(MF);
|
||||
// Convert register index to 256-byte unit.
|
||||
uint64_t StackOffset = IndirectBegin < 0 ? 0 : (4 * IndirectBegin / 256);
|
||||
|
||||
assert((StackSizeBytes < 0xffff) && StackOffset < 0xffff &&
|
||||
"Stack limits should be smaller than 16-bits");
|
||||
|
||||
// Initialize the flat scratch register pair.
|
||||
// TODO: Can we use one s_mov_b64 here?
|
||||
|
||||
// Offset is in units of 256-bytes.
|
||||
MachineBasicBlock &MBB = MF.front();
|
||||
DebugLoc NoDL;
|
||||
MachineBasicBlock::iterator Start = MBB.getFirstNonPHI();
|
||||
const MCInstrDesc &SMovK = TII->get(AMDGPU::S_MOVK_I32);
|
||||
|
||||
BuildMI(MBB, Start, NoDL, SMovK, AMDGPU::FLAT_SCR_LO)
|
||||
.addImm(StackOffset);
|
||||
|
||||
// Documentation says size is "per-thread scratch size in bytes"
|
||||
BuildMI(MBB, Start, NoDL, SMovK, AMDGPU::FLAT_SCR_HI)
|
||||
.addImm(StackSizeBytes);
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -33,6 +33,7 @@ BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
|
|||
BitVector Reserved(getNumRegs());
|
||||
Reserved.set(AMDGPU::EXEC);
|
||||
Reserved.set(AMDGPU::INDIRECT_BASE_ADDR);
|
||||
Reserved.set(AMDGPU::FLAT_SCR);
|
||||
return Reserved;
|
||||
}
|
||||
|
||||
|
|
@ -246,6 +247,28 @@ unsigned SIRegisterInfo::getPhysRegSubReg(unsigned Reg,
|
|||
default: llvm_unreachable("Invalid SubIdx for VCC");
|
||||
}
|
||||
break;
|
||||
|
||||
case AMDGPU::FLAT_SCR:
|
||||
switch (Channel) {
|
||||
case 0:
|
||||
return AMDGPU::FLAT_SCR_LO;
|
||||
case 1:
|
||||
return AMDGPU::FLAT_SCR_HI;
|
||||
default:
|
||||
llvm_unreachable("Invalid SubIdx for FLAT_SCR");
|
||||
}
|
||||
break;
|
||||
|
||||
case AMDGPU::EXEC:
|
||||
switch (Channel) {
|
||||
case 0:
|
||||
return AMDGPU::EXEC_LO;
|
||||
case 1:
|
||||
return AMDGPU::EXEC_HI;
|
||||
default:
|
||||
llvm_unreachable("Invalid SubIdx for EXEC");
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
unsigned Index = getHWRegIndex(Reg);
|
||||
|
|
|
|||
|
|
@ -39,6 +39,16 @@ def EXEC : RegisterWithSubRegs<"EXEC", [EXEC_LO, EXEC_HI]> {
|
|||
def SCC : SIReg<"SCC", 253>;
|
||||
def M0 : SIReg <"M0", 124>;
|
||||
|
||||
def FLAT_SCR_LO : SIReg<"flat_scr_lo", 104>; // Offset in units of 256-bytes.
|
||||
def FLAT_SCR_HI : SIReg<"flat_scr_hi", 105>; // Size is the per-thread scratch size, in bytes.
|
||||
|
||||
// Pair to indicate location of scratch space for flat accesses.
|
||||
def FLAT_SCR : RegisterWithSubRegs <"FLAT_SCR", [FLAT_SCR_LO, FLAT_SCR_HI]> {
|
||||
let Namespace = "AMDGPU";
|
||||
let SubRegIndices = [sub0, sub1];
|
||||
let HWEncoding = 104;
|
||||
}
|
||||
|
||||
// SGPR registers
|
||||
foreach Index = 0-101 in {
|
||||
def SGPR#Index : SIReg <"SGPR"#Index, Index>;
|
||||
|
|
@ -167,13 +177,13 @@ def M0Reg : RegisterClass<"AMDGPU", [i32], 32, (add M0)>;
|
|||
|
||||
// Register class for all scalar registers (SGPRs + Special Registers)
|
||||
def SReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
|
||||
(add SGPR_32, M0Reg, VCC_LO, VCC_HI, EXEC_LO, EXEC_HI)
|
||||
(add SGPR_32, M0Reg, VCC_LO, VCC_HI, EXEC_LO, EXEC_HI, FLAT_SCR_LO, FLAT_SCR_HI)
|
||||
>;
|
||||
|
||||
def SGPR_64 : RegisterClass<"AMDGPU", [v2i32, i64], 64, (add SGPR_64Regs)>;
|
||||
|
||||
def SReg_64 : RegisterClass<"AMDGPU", [v2i32, i64, i1], 64,
|
||||
(add SGPR_64, VCCReg, EXECReg)
|
||||
(add SGPR_64, VCCReg, EXECReg, FLAT_SCR)
|
||||
>;
|
||||
|
||||
def SReg_128 : RegisterClass<"AMDGPU", [v4i32, v16i8], 128, (add SGPR_128)>;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,182 @@
|
|||
; RUN: llc -O0 -march=r600 -mcpu=bonaire -mattr=-promote-alloca < %s | FileCheck -check-prefix=CHECK -check-prefix=CHECK-NO-PROMOTE %s
|
||||
; RUN: llc -O0 -march=r600 -mcpu=bonaire -mattr=+promote-alloca < %s | FileCheck -check-prefix=CHECK -check-prefix=CHECK-PROMOTE %s
|
||||
|
||||
; Disable optimizations in case there are optimizations added that
|
||||
; specialize away generic pointer accesses.
|
||||
|
||||
|
||||
; CHECK-LABEL: @branch_use_flat_i32:
|
||||
; CHECK: FLAT_STORE_DWORD {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, [M0, FLAT_SCRATCH]
|
||||
; CHECK: S_ENDPGM
|
||||
define void @branch_use_flat_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* %gptr, i32 addrspace(3)* %lptr, i32 %x, i32 %c) #0 {
|
||||
entry:
|
||||
%cmp = icmp ne i32 %c, 0
|
||||
br i1 %cmp, label %local, label %global
|
||||
|
||||
local:
|
||||
%flat_local = addrspacecast i32 addrspace(3)* %lptr to i32 addrspace(4)*
|
||||
br label %end
|
||||
|
||||
global:
|
||||
%flat_global = addrspacecast i32 addrspace(1)* %gptr to i32 addrspace(4)*
|
||||
br label %end
|
||||
|
||||
end:
|
||||
%fptr = phi i32 addrspace(4)* [ %flat_local, %local ], [ %flat_global, %global ]
|
||||
store i32 %x, i32 addrspace(4)* %fptr, align 4
|
||||
; %val = load i32 addrspace(4)* %fptr, align 4
|
||||
; store i32 %val, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
|
||||
; These testcases might become useless when there are optimizations to
|
||||
; remove generic pointers.
|
||||
|
||||
; CHECK-LABEL: @store_flat_i32:
|
||||
; CHECK: V_MOV_B32_e32 v[[DATA:[0-9]+]], {{s[0-9]+}}
|
||||
; CHECK: V_MOV_B32_e32 v[[LO_VREG:[0-9]+]], {{s[0-9]+}}
|
||||
; CHECK: V_MOV_B32_e32 v[[HI_VREG:[0-9]+]], {{s[0-9]+}}
|
||||
; CHECK: FLAT_STORE_DWORD v[[DATA]], v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}
|
||||
define void @store_flat_i32(i32 addrspace(1)* %gptr, i32 %x) #0 {
|
||||
%fptr = addrspacecast i32 addrspace(1)* %gptr to i32 addrspace(4)*
|
||||
store i32 %x, i32 addrspace(4)* %fptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @store_flat_i64:
|
||||
; CHECK: FLAT_STORE_DWORDX2
|
||||
define void @store_flat_i64(i64 addrspace(1)* %gptr, i64 %x) #0 {
|
||||
%fptr = addrspacecast i64 addrspace(1)* %gptr to i64 addrspace(4)*
|
||||
store i64 %x, i64 addrspace(4)* %fptr, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @store_flat_v4i32:
|
||||
; CHECK: FLAT_STORE_DWORDX4
|
||||
define void @store_flat_v4i32(<4 x i32> addrspace(1)* %gptr, <4 x i32> %x) #0 {
|
||||
%fptr = addrspacecast <4 x i32> addrspace(1)* %gptr to <4 x i32> addrspace(4)*
|
||||
store <4 x i32> %x, <4 x i32> addrspace(4)* %fptr, align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @store_flat_trunc_i16:
|
||||
; CHECK: FLAT_STORE_SHORT
|
||||
define void @store_flat_trunc_i16(i16 addrspace(1)* %gptr, i32 %x) #0 {
|
||||
%fptr = addrspacecast i16 addrspace(1)* %gptr to i16 addrspace(4)*
|
||||
%y = trunc i32 %x to i16
|
||||
store i16 %y, i16 addrspace(4)* %fptr, align 2
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @store_flat_trunc_i8:
|
||||
; CHECK: FLAT_STORE_BYTE
|
||||
define void @store_flat_trunc_i8(i8 addrspace(1)* %gptr, i32 %x) #0 {
|
||||
%fptr = addrspacecast i8 addrspace(1)* %gptr to i8 addrspace(4)*
|
||||
%y = trunc i32 %x to i8
|
||||
store i8 %y, i8 addrspace(4)* %fptr, align 2
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
|
||||
; CHECK-LABEL @load_flat_i32:
|
||||
; CHECK: FLAT_LOAD_DWORD
|
||||
define void @load_flat_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %gptr) #0 {
|
||||
%fptr = addrspacecast i32 addrspace(1)* %gptr to i32 addrspace(4)*
|
||||
%fload = load i32 addrspace(4)* %fptr, align 4
|
||||
store i32 %fload, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL @load_flat_i64:
|
||||
; CHECK: FLAT_LOAD_DWORDX2
|
||||
define void @load_flat_i64(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %gptr) #0 {
|
||||
%fptr = addrspacecast i64 addrspace(1)* %gptr to i64 addrspace(4)*
|
||||
%fload = load i64 addrspace(4)* %fptr, align 4
|
||||
store i64 %fload, i64 addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL @load_flat_v4i32:
|
||||
; CHECK: FLAT_LOAD_DWORDX4
|
||||
define void @load_flat_v4i32(<4 x i32> addrspace(1)* noalias %out, <4 x i32> addrspace(1)* noalias %gptr) #0 {
|
||||
%fptr = addrspacecast <4 x i32> addrspace(1)* %gptr to <4 x i32> addrspace(4)*
|
||||
%fload = load <4 x i32> addrspace(4)* %fptr, align 4
|
||||
store <4 x i32> %fload, <4 x i32> addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL @sextload_flat_i8:
|
||||
; CHECK: FLAT_LOAD_SBYTE
|
||||
define void @sextload_flat_i8(i32 addrspace(1)* noalias %out, i8 addrspace(1)* noalias %gptr) #0 {
|
||||
%fptr = addrspacecast i8 addrspace(1)* %gptr to i8 addrspace(4)*
|
||||
%fload = load i8 addrspace(4)* %fptr, align 4
|
||||
%ext = sext i8 %fload to i32
|
||||
store i32 %ext, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL @zextload_flat_i8:
|
||||
; CHECK: FLAT_LOAD_UBYTE
|
||||
define void @zextload_flat_i8(i32 addrspace(1)* noalias %out, i8 addrspace(1)* noalias %gptr) #0 {
|
||||
%fptr = addrspacecast i8 addrspace(1)* %gptr to i8 addrspace(4)*
|
||||
%fload = load i8 addrspace(4)* %fptr, align 4
|
||||
%ext = zext i8 %fload to i32
|
||||
store i32 %ext, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL @sextload_flat_i16:
|
||||
; CHECK: FLAT_LOAD_SSHORT
|
||||
define void @sextload_flat_i16(i32 addrspace(1)* noalias %out, i16 addrspace(1)* noalias %gptr) #0 {
|
||||
%fptr = addrspacecast i16 addrspace(1)* %gptr to i16 addrspace(4)*
|
||||
%fload = load i16 addrspace(4)* %fptr, align 4
|
||||
%ext = sext i16 %fload to i32
|
||||
store i32 %ext, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL @zextload_flat_i16:
|
||||
; CHECK: FLAT_LOAD_USHORT
|
||||
define void @zextload_flat_i16(i32 addrspace(1)* noalias %out, i16 addrspace(1)* noalias %gptr) #0 {
|
||||
%fptr = addrspacecast i16 addrspace(1)* %gptr to i16 addrspace(4)*
|
||||
%fload = load i16 addrspace(4)* %fptr, align 4
|
||||
%ext = zext i16 %fload to i32
|
||||
store i32 %ext, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
|
||||
; TODO: This should not be zero when registers are used for small
|
||||
; scratch allocations again.
|
||||
|
||||
; Check for prologue initializing special SGPRs pointing to scratch.
|
||||
; CHECK-LABEL: @store_flat_scratch:
|
||||
; CHECK: S_MOVK_I32 flat_scratch_lo, 0
|
||||
; CHECK-NO-PROMOTE: S_MOVK_I32 flat_scratch_hi, 40
|
||||
; CHECK-PROMOTE: S_MOVK_I32 flat_scratch_hi, 0
|
||||
; CHECK: FLAT_STORE_DWORD
|
||||
; CHECK: S_BARRIER
|
||||
; CHECK: FLAT_LOAD_DWORD
|
||||
define void @store_flat_scratch(i32 addrspace(1)* noalias %out, i32) #0 {
|
||||
%alloca = alloca i32, i32 9, align 4
|
||||
%x = call i32 @llvm.r600.read.tidig.x() #3
|
||||
%pptr = getelementptr i32* %alloca, i32 %x
|
||||
%fptr = addrspacecast i32* %pptr to i32 addrspace(4)*
|
||||
store i32 %x, i32 addrspace(4)* %fptr
|
||||
; Dummy call
|
||||
call void @llvm.AMDGPU.barrier.local() #1
|
||||
%reload = load i32 addrspace(4)* %fptr, align 4
|
||||
store i32 %reload, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
declare void @llvm.AMDGPU.barrier.local() #1
|
||||
declare i32 @llvm.r600.read.tidig.x() #3
|
||||
|
||||
attributes #0 = { nounwind }
|
||||
attributes #1 = { nounwind noduplicate }
|
||||
attributes #3 = { nounwind readnone }
|
||||
Loading…
Reference in New Issue