diff --git a/llvm/lib/Bitcode/Writer/ValueEnumerator.cpp b/llvm/lib/Bitcode/Writer/ValueEnumerator.cpp
index 273ea06c641d..f0f9f7430c53 100644
--- a/llvm/lib/Bitcode/Writer/ValueEnumerator.cpp
+++ b/llvm/lib/Bitcode/Writer/ValueEnumerator.cpp
@@ -106,6 +106,9 @@ static void predictValueUseListOrderImpl(const Value *V, const Function *F,
             [&OM, ID](const Entry &L, const Entry &R) {
     const Use *LU = L.first;
     const Use *RU = R.first;
+    if (LU == RU)
+      return false;
+
     auto LID = OM.lookup(LU->getUser()).first;
     auto RID = OM.lookup(RU->getUser()).first;
     // If ID is 4, then expect: 7 6 5 1 2 3.
diff --git a/llvm/test/Bitcode/2006-12-11-Cast-ConstExpr.ll b/llvm/test/Bitcode/2006-12-11-Cast-ConstExpr.ll
index e704627e3610..e1e2d7dc5447 100644
--- a/llvm/test/Bitcode/2006-12-11-Cast-ConstExpr.ll
+++ b/llvm/test/Bitcode/2006-12-11-Cast-ConstExpr.ll
@@ -1,6 +1,7 @@
 ; This test ensures that we get a bitcast constant expression in and out,
 ; not a sitofp constant expression. 
 ; RUN: llvm-as < %s | llvm-dis | FileCheck %s
+; RUN: llvm-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
 ; CHECK: bitcast (
 
 @G = external global i32
diff --git a/llvm/test/Bitcode/2009-06-11-FirstClassAggregateConstant.ll b/llvm/test/Bitcode/2009-06-11-FirstClassAggregateConstant.ll
index 415f88e16374..a321ce213113 100644
--- a/llvm/test/Bitcode/2009-06-11-FirstClassAggregateConstant.ll
+++ b/llvm/test/Bitcode/2009-06-11-FirstClassAggregateConstant.ll
@@ -1,4 +1,5 @@
 ; RUN: llvm-as < %s | llvm-dis -disable-output
+; RUN: llvm-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
 ; PR4373
 
 @foo = weak global { i32 } zeroinitializer              
diff --git a/llvm/test/Bitcode/aggregateInstructions.3.2.ll b/llvm/test/Bitcode/aggregateInstructions.3.2.ll
index 8d9378c363f4..4d35be08bd12 100644
--- a/llvm/test/Bitcode/aggregateInstructions.3.2.ll
+++ b/llvm/test/Bitcode/aggregateInstructions.3.2.ll
@@ -1,4 +1,5 @@
 ; RUN: llvm-dis < %s.bc| FileCheck %s
+; RUN: llvm-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
 
 ; aggregateOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
 ; The test checks that LLVM does not misread instructions with aggregate operands
diff --git a/llvm/test/Bitcode/arm32_neon_vcnt_upgrade.ll b/llvm/test/Bitcode/arm32_neon_vcnt_upgrade.ll
index 10b9284e9814..fba518fe7f7f 100644
--- a/llvm/test/Bitcode/arm32_neon_vcnt_upgrade.ll
+++ b/llvm/test/Bitcode/arm32_neon_vcnt_upgrade.ll
@@ -1,4 +1,5 @@
 ; RUN: llvm-as < %s | llvm-dis | FileCheck %s
+; RUN: llvm-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
 ; Tests vclz and vcnt
 
 define <4 x i16> @vclz16(<4 x i16>* %A) nounwind {
diff --git a/llvm/test/Bitcode/atomic.ll b/llvm/test/Bitcode/atomic.ll
index d41c9e7acf72..448219a59cb4 100644
--- a/llvm/test/Bitcode/atomic.ll
+++ b/llvm/test/Bitcode/atomic.ll
@@ -1,4 +1,5 @@
 ; RUN: llvm-as %s -o - | llvm-dis | FileCheck %s
+; RUN: llvm-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
 
 define void @test_cmpxchg(i32* %addr, i32 %desired, i32 %new) {
   cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst seq_cst
diff --git a/llvm/test/Bitcode/attributes-3.3.ll b/llvm/test/Bitcode/attributes-3.3.ll
index cd70ba1a749a..7b44938a3e82 100644
--- a/llvm/test/Bitcode/attributes-3.3.ll
+++ b/llvm/test/Bitcode/attributes-3.3.ll
@@ -1,4 +1,5 @@
 ; RUN:  llvm-dis < %s.bc| FileCheck %s
+; RUN:  llvm-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
 
 ; attributes-3.3.ll.bc was generated by passing this file to llvm-as-3.3.
 ; The test checks that LLVM does not silently misread attributes of
diff --git a/llvm/test/Bitcode/attributes.ll b/llvm/test/Bitcode/attributes.ll
index 9a429f6e21f7..0fe66f5ad82c 100644
--- a/llvm/test/Bitcode/attributes.ll
+++ b/llvm/test/Bitcode/attributes.ll
@@ -1,4 +1,5 @@
 ; RUN: llvm-as < %s | llvm-dis | FileCheck %s
+; RUN: llvm-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
 ; PR12696
 
 define void @f1(i8 zeroext)
diff --git a/llvm/test/Bitcode/binaryFloatInstructions.3.2.ll b/llvm/test/Bitcode/binaryFloatInstructions.3.2.ll
index ef0b03dbe544..a0010e03834d 100644
--- a/llvm/test/Bitcode/binaryFloatInstructions.3.2.ll
+++ b/llvm/test/Bitcode/binaryFloatInstructions.3.2.ll
@@ -1,4 +1,5 @@
 ; RUN: llvm-dis < %s.bc| FileCheck %s
+; RUN: llvm-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
 
 ; BinaryFloatOperation.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
 ; The test checks that LLVM does not misread binary float instructions from
diff --git a/llvm/test/Bitcode/binaryIntInstructions.3.2.ll b/llvm/test/Bitcode/binaryIntInstructions.3.2.ll
index 2856c13f8907..bcf3d5882e05 100644
--- a/llvm/test/Bitcode/binaryIntInstructions.3.2.ll
+++ b/llvm/test/Bitcode/binaryIntInstructions.3.2.ll
@@ -1,4 +1,5 @@
 ; RUN: llvm-dis < %s.bc| FileCheck %s
+; RUN: llvm-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
 
 ; BinaryIntOperation.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
 ; The test checks that LLVM does not misread binary integer instructions from
diff --git a/llvm/test/Bitcode/bitwiseInstructions.3.2.ll b/llvm/test/Bitcode/bitwiseInstructions.3.2.ll
index a8ca963f62aa..780f0447a52c 100644
--- a/llvm/test/Bitcode/bitwiseInstructions.3.2.ll
+++ b/llvm/test/Bitcode/bitwiseInstructions.3.2.ll
@@ -1,4 +1,5 @@
 ; RUN: llvm-dis < %s.bc| FileCheck %s
+; RUN: llvm-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
 
 ; bitwiseOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
 ; The test checks that LLVM does not misread bitwise instructions from
diff --git a/llvm/test/Bitcode/calling-conventions.3.2.ll b/llvm/test/Bitcode/calling-conventions.3.2.ll
index aca9efd0892b..6a497dc8d5a8 100644
--- a/llvm/test/Bitcode/calling-conventions.3.2.ll
+++ b/llvm/test/Bitcode/calling-conventions.3.2.ll
@@ -1,4 +1,5 @@
 ; RUN:  llvm-dis < %s.bc| FileCheck %s
+; RUN:  llvm-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
 
 ; calling-conventions.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
 ; The test checks that LLVM does not silently misread calling conventions of
diff --git a/llvm/test/Bitcode/case-ranges-3.3.ll b/llvm/test/Bitcode/case-ranges-3.3.ll
index 6e1d0a69a591..1198f2bb2cb8 100644
--- a/llvm/test/Bitcode/case-ranges-3.3.ll
+++ b/llvm/test/Bitcode/case-ranges-3.3.ll
@@ -1,4 +1,5 @@
 ; RUN:  llvm-dis < %s.bc| FileCheck %s
+; RUN:  llvm-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
 
 ; case-ranges.ll.bc was generated by passing this file to llvm-as from the 3.3
 ; release of LLVM. This tests that the bitcode for switches from that release
diff --git a/llvm/test/Bitcode/cmpxchg-upgrade.ll b/llvm/test/Bitcode/cmpxchg-upgrade.ll
index eae62b074546..94f0eef455e6 100644
--- a/llvm/test/Bitcode/cmpxchg-upgrade.ll
+++ b/llvm/test/Bitcode/cmpxchg-upgrade.ll
@@ -1,4 +1,5 @@
 ; RUN: llvm-dis < %s.bc | FileCheck %s
+; RUN: llvm-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
 
 ; cmpxchg-upgrade.ll.bc was produced by running a version of llvm-as from just
 ; before the IR change on this file.
diff --git a/llvm/test/Bitcode/conversionInstructions.3.2.ll b/llvm/test/Bitcode/conversionInstructions.3.2.ll
index 245388500a06..9f8204821d4d 100644
--- a/llvm/test/Bitcode/conversionInstructions.3.2.ll
+++ b/llvm/test/Bitcode/conversionInstructions.3.2.ll
@@ -1,4 +1,5 @@
 ; RUN: llvm-dis < %s.bc| FileCheck %s
+; RUN: llvm-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
 
 ; conversionOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
 ; The test checks that LLVM does not misread conversion instructions from
diff --git a/llvm/test/Bitcode/drop-debug-info.ll b/llvm/test/Bitcode/drop-debug-info.ll
index 5123018577ee..b3073e0d6c8b 100644
--- a/llvm/test/Bitcode/drop-debug-info.ll
+++ b/llvm/test/Bitcode/drop-debug-info.ll
@@ -1,5 +1,6 @@
 ; RUN: llvm-as < %s -o %t.bc 2>&1 >/dev/null | FileCheck -check-prefix=WARN %s
 ; RUN: llvm-dis < %t.bc | FileCheck %s
+; RUN: llvm-uselistorder < %t.bc -preserve-bc-use-list-order -num-shuffles=5
 
 define i32 @main() {
 entry:
diff --git a/llvm/test/Bitcode/extractelement.ll b/llvm/test/Bitcode/extractelement.ll
index 8999c656fce9..29f5b029200c 100644
--- a/llvm/test/Bitcode/extractelement.ll
+++ b/llvm/test/Bitcode/extractelement.ll
@@ -1,4 +1,5 @@
 ; RUN: opt < %s -constprop | llvm-dis -disable-output
+; RUN: llvm-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
 ; PR3465
 
 define double @test() {
diff --git a/llvm/test/Bitcode/flags.ll b/llvm/test/Bitcode/flags.ll
index 7b0c5b538894..3760a44bd6fd 100644
--- a/llvm/test/Bitcode/flags.ll
+++ b/llvm/test/Bitcode/flags.ll
@@ -1,6 +1,7 @@
 ; RUN: llvm-as < %s | llvm-dis > %t0
 ; RUN: opt -S < %s > %t1
 ; RUN: diff %t0 %t1
+; RUN: llvm-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
 ; PR6140
 
 ; Make sure the flags are serialized/deserialized properly for both
diff --git a/llvm/test/Bitcode/function-encoding-rel-operands.ll b/llvm/test/Bitcode/function-encoding-rel-operands.ll
index aedb0c32676f..cc2f6aef5e5b 100644
--- a/llvm/test/Bitcode/function-encoding-rel-operands.ll
+++ b/llvm/test/Bitcode/function-encoding-rel-operands.ll
@@ -1,6 +1,7 @@
 ; Basic sanity test to check that instruction operands are encoded with
 ; relative IDs.
 ; RUN: llvm-as < %s | llvm-bcanalyzer -dump | FileCheck %s
+; RUN: llvm-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
 
 ; CHECK: FUNCTION_BLOCK
 ; CHECK: INST_BINOP {{.*}}op0=1 op1=1
diff --git a/llvm/test/Bitcode/global-variables.3.2.ll b/llvm/test/Bitcode/global-variables.3.2.ll
index 549d025549be..4a856f199e58 100644
--- a/llvm/test/Bitcode/global-variables.3.2.ll
+++ b/llvm/test/Bitcode/global-variables.3.2.ll
@@ -1,4 +1,5 @@
 ; RUN:  llvm-dis < %s.bc| FileCheck %s
+; RUN:  llvm-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
 
 ; global-variables.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
 ; The test checks that LLVM does not silently misread global variables attributes of
diff --git a/llvm/test/Bitcode/inalloca.ll b/llvm/test/Bitcode/inalloca.ll
index bad87a9b03f0..445b4a282bff 100644
--- a/llvm/test/Bitcode/inalloca.ll
+++ b/llvm/test/Bitcode/inalloca.ll
@@ -1,4 +1,5 @@
 ; RUN: llvm-as < %s | llvm-dis | FileCheck %s
+; RUN: llvm-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
 
 ; inalloca should roundtrip.
 
diff --git a/llvm/test/Bitcode/linkage-types-3.2.ll b/llvm/test/Bitcode/linkage-types-3.2.ll
index fd070efbd444..01b195f6c51a 100644
--- a/llvm/test/Bitcode/linkage-types-3.2.ll
+++ b/llvm/test/Bitcode/linkage-types-3.2.ll
@@ -1,4 +1,5 @@
 ; RUN:  llvm-dis < %s.bc| FileCheck %s
+; RUN:  llvm-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
 
 ; linkage-types-3.2.ll.bc was generated by passing this file to llvm-as-3.2
 ; The test checks that LLVM does not silently misread linkage types of
diff --git a/llvm/test/Bitcode/memInstructions.3.2.ll b/llvm/test/Bitcode/memInstructions.3.2.ll
index a84f8c3d84e3..a8073225a69c 100644
--- a/llvm/test/Bitcode/memInstructions.3.2.ll
+++ b/llvm/test/Bitcode/memInstructions.3.2.ll
@@ -1,4 +1,5 @@
 ; RUN: llvm-dis < %s.bc| FileCheck %s
+; RUN: llvm-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
 
 ; memOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
 ; The test checks that LLVM does not misread memory related instructions of
diff --git a/llvm/test/Bitcode/metadata.ll b/llvm/test/Bitcode/metadata.ll
index fc8a622252bf..a3550bcaceca 100644
--- a/llvm/test/Bitcode/metadata.ll
+++ b/llvm/test/Bitcode/metadata.ll
@@ -1,4 +1,5 @@
 ; RUN: llvm-as < %s | llvm-dis -disable-output
+; RUN: llvm-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
 
 !llvm.foo = !{!0}
 !0 = metadata !{i32 42}
diff --git a/llvm/test/Bitcode/ptest-new.ll b/llvm/test/Bitcode/ptest-new.ll
index 735cc9c1cc44..c0ded8b622c0 100644
--- a/llvm/test/Bitcode/ptest-new.ll
+++ b/llvm/test/Bitcode/ptest-new.ll
@@ -1,4 +1,5 @@
 ; RUN: llvm-as < %s | llvm-dis | FileCheck %s
+; RUN: llvm-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
 
 define i32 @foo(<2 x i64> %bar) nounwind {
 entry:
diff --git a/llvm/test/Bitcode/ptest-old.ll b/llvm/test/Bitcode/ptest-old.ll
index fbe962fae51a..c6c160539c21 100644
--- a/llvm/test/Bitcode/ptest-old.ll
+++ b/llvm/test/Bitcode/ptest-old.ll
@@ -1,4 +1,5 @@
 ; RUN: llvm-as < %s | llvm-dis | FileCheck %s
+; RUN: llvm-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
 
 define i32 @foo(<4 x float> %bar) nounwind {
 entry:
diff --git a/llvm/test/Bitcode/select.ll b/llvm/test/Bitcode/select.ll
index 08a3061394db..3da538578706 100644
--- a/llvm/test/Bitcode/select.ll
+++ b/llvm/test/Bitcode/select.ll
@@ -1,4 +1,5 @@
 ; RUN: llvm-as < %s | llvm-dis | FileCheck %s
+; RUN: llvm-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
 
 define <2 x i32> @main() {
   ret <2 x i32> select (<2 x i1> <i1 false, i1 undef>, <2 x i32> zeroinitializer, <2 x i32> <i32 0, i32 undef>)
diff --git a/llvm/test/Bitcode/shuffle.ll b/llvm/test/Bitcode/shuffle.ll
index 1495d8eebf9c..65bde6765c26 100644
--- a/llvm/test/Bitcode/shuffle.ll
+++ b/llvm/test/Bitcode/shuffle.ll
@@ -1,4 +1,5 @@
 ; RUN: llvm-as < %s | llvm-dis -disable-output
+; RUN: llvm-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
 
 ; <rdar://problem/8622574>
 ; tests the bitcodereader can handle the case where the reader will initially
diff --git a/llvm/test/Bitcode/tailcall.ll b/llvm/test/Bitcode/tailcall.ll
index 765b47054cad..ea47df62011a 100644
--- a/llvm/test/Bitcode/tailcall.ll
+++ b/llvm/test/Bitcode/tailcall.ll
@@ -1,4 +1,5 @@
 ; RUN: llvm-as < %s | llvm-dis | FileCheck %s
+; RUN: llvm-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
 
 ; Check that musttail and tail roundtrip.
 
diff --git a/llvm/test/Bitcode/terminatorInstructions.3.2.ll b/llvm/test/Bitcode/terminatorInstructions.3.2.ll
index 9c70833ae615..d9e51a5996e8 100644
--- a/llvm/test/Bitcode/terminatorInstructions.3.2.ll
+++ b/llvm/test/Bitcode/terminatorInstructions.3.2.ll
@@ -1,4 +1,5 @@
 ; RUN: llvm-dis < %s.bc| FileCheck %s
+; RUN: llvm-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
 
 ; TerminatorOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
 ; The test checks that LLVM does not misread terminator instructions from
diff --git a/llvm/test/Bitcode/upgrade-global-ctors.ll b/llvm/test/Bitcode/upgrade-global-ctors.ll
index bd253a81620f..f75b28b7db1e 100644
--- a/llvm/test/Bitcode/upgrade-global-ctors.ll
+++ b/llvm/test/Bitcode/upgrade-global-ctors.ll
@@ -1,3 +1,4 @@
 ; RUN:  llvm-dis < %s.bc| FileCheck %s
+; RUN:  llvm-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
 
 ; CHECK: @llvm.global_ctors = appending global [0 x { i32, void ()*, i8* }] zeroinitializer
diff --git a/llvm/test/Bitcode/upgrade-loop-metadata.ll b/llvm/test/Bitcode/upgrade-loop-metadata.ll
index 67a8d3935926..5c18bd930cc2 100644
--- a/llvm/test/Bitcode/upgrade-loop-metadata.ll
+++ b/llvm/test/Bitcode/upgrade-loop-metadata.ll
@@ -1,6 +1,7 @@
 ; Test to make sure loop vectorizer metadata is automatically upgraded.
 ;
 ; RUN: llvm-dis < %s.bc | FileCheck %s
+; RUN: llvm-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
 
 define void @_Z28loop_with_vectorize_metadatav() {
 entry:
diff --git a/llvm/test/Bitcode/upgrade-tbaa.ll b/llvm/test/Bitcode/upgrade-tbaa.ll
index e7389095b8c1..0d88fa6ce3a7 100644
--- a/llvm/test/Bitcode/upgrade-tbaa.ll
+++ b/llvm/test/Bitcode/upgrade-tbaa.ll
@@ -1,4 +1,5 @@
 ; RUN: llvm-as < %s | llvm-dis | FileCheck %s
+; RUN: llvm-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
 
 ; Function Attrs: nounwind
 define void @_Z4testPiPf(i32* nocapture %pI, float* nocapture %pF) #0 {
diff --git a/llvm/test/Bitcode/vectorInstructions.3.2.ll b/llvm/test/Bitcode/vectorInstructions.3.2.ll
index 6d534c2f1438..5b983ac0f02e 100644
--- a/llvm/test/Bitcode/vectorInstructions.3.2.ll
+++ b/llvm/test/Bitcode/vectorInstructions.3.2.ll
@@ -1,4 +1,5 @@
 ; RUN: llvm-dis < %s.bc| FileCheck %s
+; RUN: llvm-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
 
 ; vectorOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
 ; The test checks that LLVM does not misread vector operations of
diff --git a/llvm/test/Bitcode/visibility-styles.3.2.ll b/llvm/test/Bitcode/visibility-styles.3.2.ll
index ec2ee6832063..cccc9509e67a 100644
--- a/llvm/test/Bitcode/visibility-styles.3.2.ll
+++ b/llvm/test/Bitcode/visibility-styles.3.2.ll
@@ -1,4 +1,5 @@
 ; RUN:  llvm-dis < %s.bc| FileCheck %s
+; RUN:  llvm-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
 
 ; visibility-styles.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
 ; The test checks that LLVM does not silently misread visibility styles of
diff --git a/llvm/test/Bitcode/weak-cmpxchg-upgrade.ll b/llvm/test/Bitcode/weak-cmpxchg-upgrade.ll
index dbcd150633ed..fd543c4a9685 100644
--- a/llvm/test/Bitcode/weak-cmpxchg-upgrade.ll
+++ b/llvm/test/Bitcode/weak-cmpxchg-upgrade.ll
@@ -1,4 +1,5 @@
 ; RUN: llvm-dis < %s.bc | FileCheck %s
+; RUN: llvm-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
 
 ; cmpxchg-upgrade.ll.bc was produced by running a version of llvm-as from just
 ; before the IR change on this file.