parent
5a32c7647e
commit
3ec882feed
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@ -158,7 +158,7 @@ INITIALIZE_PASS_END(AArch64A57FPLoadBalancing, DEBUG_TYPE,
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"AArch64 A57 FP Load-Balancing", false, false)
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"AArch64 A57 FP Load-Balancing", false, false)
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namespace {
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namespace {
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/// A Chain is a sequence of instructions that are linked together by
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/// A Chain is a sequence of instructions that are linked together by
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/// an accumulation operand. For example:
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/// an accumulation operand. For example:
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///
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///
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/// fmul d0<def>, ?
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/// fmul d0<def>, ?
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@ -285,7 +285,7 @@ public:
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std::string str() const {
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std::string str() const {
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std::string S;
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std::string S;
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raw_string_ostream OS(S);
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raw_string_ostream OS(S);
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OS << "{";
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OS << "{";
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StartInst->print(OS, /* SkipOpers= */true);
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StartInst->print(OS, /* SkipOpers= */true);
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OS << " -> ";
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OS << " -> ";
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@ -427,7 +427,7 @@ Chain *AArch64A57FPLoadBalancing::getAndEraseNext(Color PreferredColor,
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return Ch;
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return Ch;
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}
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}
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}
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}
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// Bailout case - just return the first item.
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// Bailout case - just return the first item.
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Chain *Ch = L.front();
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Chain *Ch = L.front();
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L.erase(L.begin());
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L.erase(L.begin());
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@ -495,7 +495,7 @@ int AArch64A57FPLoadBalancing::scavengeRegister(Chain *G, Color C,
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RS.enterBasicBlock(&MBB);
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RS.enterBasicBlock(&MBB);
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RS.forward(MachineBasicBlock::iterator(G->getStart()));
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RS.forward(MachineBasicBlock::iterator(G->getStart()));
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// Can we find an appropriate register that is available throughout the life
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// Can we find an appropriate register that is available throughout the life
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// of the chain?
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// of the chain?
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unsigned RegClassID = G->getStart()->getDesc().OpInfo[0].RegClass;
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unsigned RegClassID = G->getStart()->getDesc().OpInfo[0].RegClass;
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BitVector AvailableRegs = RS.getRegsAvailable(TRI->getRegClass(RegClassID));
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BitVector AvailableRegs = RS.getRegsAvailable(TRI->getRegClass(RegClassID));
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