diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 089d31e818eb..36f16e3ca9ab 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -3159,29 +3159,6 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op, SDValue Cast = DAG.getNode(ISD::BITCAST, DL, MVT::i32, Src); return DAG.getNode(AMDGPUISD::KILL, DL, MVT::Other, Chain, Cast); } - case AMDGPUIntrinsic::SI_export: { // Legacy intrinsic. - const ConstantSDNode *En = cast(Op.getOperand(2)); - const ConstantSDNode *VM = cast(Op.getOperand(3)); - const ConstantSDNode *Done = cast(Op.getOperand(4)); - const ConstantSDNode *Tgt = cast(Op.getOperand(5)); - const ConstantSDNode *Compr = cast(Op.getOperand(6)); - - const SDValue Ops[] = { - Chain, - DAG.getTargetConstant(Tgt->getZExtValue(), DL, MVT::i8), - DAG.getTargetConstant(En->getZExtValue(), DL, MVT::i8), - Op.getOperand(7), // src0 - Op.getOperand(8), // src1 - Op.getOperand(9), // src2 - Op.getOperand(10), // src3 - DAG.getTargetConstant(Compr->getZExtValue(), DL, MVT::i1), - DAG.getTargetConstant(VM->getZExtValue(), DL, MVT::i1) - }; - - unsigned Opc = Done->isNullValue() ? - AMDGPUISD::EXPORT : AMDGPUISD::EXPORT_DONE; - return DAG.getNode(Opc, DL, Op->getVTList(), Ops); - } default: return Op; } diff --git a/llvm/lib/Target/AMDGPU/SIIntrinsics.td b/llvm/lib/Target/AMDGPU/SIIntrinsics.td index 1fab017f99be..7b7cf1635050 100644 --- a/llvm/lib/Target/AMDGPU/SIIntrinsics.td +++ b/llvm/lib/Target/AMDGPU/SIIntrinsics.td @@ -14,19 +14,6 @@ let TargetPrefix = "SI", isTarget = 1 in { - def int_SI_export : Intrinsic <[], - [llvm_i32_ty, // en - llvm_i32_ty, // vm (FIXME: should be i1) - llvm_i32_ty, // done (FIXME: should be i1) - llvm_i32_ty, // tgt - llvm_i32_ty, // compr (FIXME: should be i1) - llvm_float_ty, // src0 - llvm_float_ty, // src1 - llvm_float_ty, // src2 - llvm_float_ty], // src3 - [] - >; - def int_SI_load_const : Intrinsic <[llvm_float_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>; // Fully-flexible TBUFFER_STORE_FORMAT_* except for the ADDR64 bit, which is not exposed diff --git a/llvm/test/CodeGen/AMDGPU/llvm.SI.export.ll b/llvm/test/CodeGen/AMDGPU/llvm.SI.export.ll deleted file mode 100644 index 2777dd12a1f2..000000000000 --- a/llvm/test/CodeGen/AMDGPU/llvm.SI.export.ll +++ /dev/null @@ -1,237 +0,0 @@ -; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=GCN %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=GCN %s - -declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) #0 - -; GCN-LABEL: {{^}}test_export_zeroes: -; GCN: exp mrt0 off, off, off, off{{$}} -; GCN: exp mrt0 off, off, off, off done{{$}} -define amdgpu_kernel void @test_export_zeroes() #0 { - - call void @llvm.SI.export(i32 0, i32 0, i32 0, i32 0, i32 0, float 0.0, float 0.0, float 0.0, float 0.0) - call void @llvm.SI.export(i32 0, i32 0, i32 1, i32 0, i32 0, float 0.0, float 0.0, float 0.0, float 0.0) - ret void -} - -; FIXME: Should not set up registers for the unused source registers. - -; GCN-LABEL: {{^}}test_export_en_src0: -; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0 -; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0 -; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5 -; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0 -; GCN: exp mrt0 [[SRC0]], off, off, off done{{$}} -define amdgpu_kernel void @test_export_en_src0() #0 { - call void @llvm.SI.export(i32 1, i32 0, i32 1, i32 0, i32 0, float 1.0, float 2.0, float 0.5, float 4.0) - ret void -} - -; GCN-LABEL: {{^}}test_export_en_src1: -; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0 -; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0 -; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5 -; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0 -; GCN: exp mrt0 off, [[SRC1]], off, off done{{$}} -define amdgpu_kernel void @test_export_en_src1() #0 { - call void @llvm.SI.export(i32 2, i32 0, i32 1, i32 0, i32 0, float 1.0, float 2.0, float 0.5, float 4.0) - ret void -} - -; GCN-LABEL: {{^}}test_export_en_src2: -; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0 -; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0 -; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5 -; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0 -; GCN: exp mrt0 off, off, [[SRC2]], off done{{$}} -define amdgpu_kernel void @test_export_en_src2() #0 { - call void @llvm.SI.export(i32 4, i32 0, i32 1, i32 0, i32 0, float 1.0, float 2.0, float 0.5, float 4.0) - ret void -} - -; GCN-LABEL: {{^}}test_export_en_src3: -; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0 -; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0 -; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5 -; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0 -; GCN: exp mrt0 off, off, off, [[SRC3]] done{{$}} -define amdgpu_kernel void @test_export_en_src3() #0 { - call void @llvm.SI.export(i32 8, i32 0, i32 1, i32 0, i32 0, float 1.0, float 2.0, float 0.5, float 4.0) - ret void -} - -; GCN-LABEL: {{^}}test_export_en_src0_src1: -; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0 -; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0 -; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5 -; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0 -; GCN: exp mrt0 [[SRC0]], [[SRC1]], off, off done{{$}} -define amdgpu_kernel void @test_export_en_src0_src1() #0 { - call void @llvm.SI.export(i32 3, i32 0, i32 1, i32 0, i32 0, float 1.0, float 2.0, float 0.5, float 4.0) - ret void -} - -; GCN-LABEL: {{^}}test_export_en_src0_src2: -; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0 -; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0 -; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5 -; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0 -; GCN: exp mrt0 [[SRC0]], off, [[SRC2]], off done{{$}} -define amdgpu_kernel void @test_export_en_src0_src2() #0 { - call void @llvm.SI.export(i32 5, i32 0, i32 1, i32 0, i32 0, float 1.0, float 2.0, float 0.5, float 4.0) - ret void -} - -; GCN-LABEL: {{^}}test_export_en_src0_src3: -; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0 -; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0 -; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5 -; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0 -; GCN: exp mrt0 [[SRC0]], off, off, [[SRC3]]{{$}} -; GCN: exp mrt0 [[SRC0]], off, off, [[SRC3]] done{{$}} -define amdgpu_kernel void @test_export_en_src0_src3() #0 { - call void @llvm.SI.export(i32 9, i32 0, i32 0, i32 0, i32 0, float 1.0, float 2.0, float 0.5, float 4.0) - call void @llvm.SI.export(i32 9, i32 0, i32 1, i32 0, i32 0, float 1.0, float 2.0, float 0.5, float 4.0) - ret void -} - -; GCN-LABEL: {{^}}test_export_en_src0_src1_src2_src3: -; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0 -; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0 -; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5 -; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0 -; GCN: exp mrt0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} -; GCN: exp mrt0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} -define amdgpu_kernel void @test_export_en_src0_src1_src2_src3() #0 { - call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 0, i32 0, float 1.0, float 2.0, float 0.5, float 4.0) - call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 0, i32 0, float 1.0, float 2.0, float 0.5, float 4.0) - ret void -} - -; GCN-LABEL: {{^}}test_export_mrt7: -; GCN-DAG: v_mov_b32_e32 [[VHALF:v[0-9]+]], 0.5 -; GCN: exp mrt7 [[VHALF]], [[VHALF]], [[VHALF]], [[VHALF]]{{$}} -; GCN: exp mrt7 [[VHALF]], [[VHALF]], [[VHALF]], [[VHALF]] done{{$}} -define amdgpu_kernel void @test_export_mrt7() #0 { - call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 7, i32 0, float 0.5, float 0.5, float 0.5, float 0.5) - call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 7, i32 0, float 0.5, float 0.5, float 0.5, float 0.5) - ret void -} - -; GCN-LABEL: {{^}}test_export_z: -; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0 -; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0 -; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5 -; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0 -; GCN: exp mrtz [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} -; GCN: exp mrtz [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} -define amdgpu_kernel void @test_export_z() #0 { - call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 8, i32 0, float 1.0, float 2.0, float 0.5, float 4.0) - call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 8, i32 0, float 1.0, float 2.0, float 0.5, float 4.0) - ret void -} - -; GCN-LABEL: {{^}}test_export_null: -; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0 -; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0 -; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5 -; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0 -; GCN: exp null [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} -; GCN: exp null [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} -define amdgpu_kernel void @test_export_null() #0 { - call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 9, i32 0, float 1.0, float 2.0, float 0.5, float 4.0) - call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 9, i32 0, float 1.0, float 2.0, float 0.5, float 4.0) - ret void -} - -; GCN-LABEL: {{^}}test_export_reserved10: -; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0 -; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0 -; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5 -; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0 -; GCN: exp invalid_target_10 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} -; GCN: exp invalid_target_10 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} -define amdgpu_kernel void @test_export_reserved10() #0 { - call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 10, i32 0, float 1.0, float 2.0, float 0.5, float 4.0) - call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 10, i32 0, float 1.0, float 2.0, float 0.5, float 4.0) - ret void -} - -; GCN-LABEL: {{^}}test_export_reserved11: -; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0 -; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0 -; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5 -; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0 -; GCN: exp invalid_target_11 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} -; GCN: exp invalid_target_11 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} -define amdgpu_kernel void @test_export_reserved11() #0 { - call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 11, i32 0, float 1.0, float 2.0, float 0.5, float 4.0) - call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 11, i32 0, float 1.0, float 2.0, float 0.5, float 4.0) - ret void -} - -; GCN-LABEL: {{^}}test_export_pos0: -; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0 -; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0 -; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5 -; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0 -; GCN: exp pos0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} -; GCN: exp pos0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} -define amdgpu_kernel void @test_export_pos0() #0 { - call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 12, i32 0, float 1.0, float 2.0, float 0.5, float 4.0) - call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float 1.0, float 2.0, float 0.5, float 4.0) - ret void -} - -; GCN-LABEL: {{^}}test_export_pos3: -; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0 -; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0 -; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5 -; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0 -; GCN: exp pos3 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} -; GCN: exp pos3 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} -define amdgpu_kernel void @test_export_pos3() #0 { - call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 15, i32 0, float 1.0, float 2.0, float 0.5, float 4.0) - call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 15, i32 0, float 1.0, float 2.0, float 0.5, float 4.0) - ret void -} - -; GCN-LABEL: {{^}}test_export_param0: -; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0 -; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0 -; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5 -; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0 -; GCN: exp param0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} -; GCN: exp param0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} -define amdgpu_kernel void @test_export_param0() #0 { - call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float 1.0, float 2.0, float 0.5, float 4.0) - call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 32, i32 0, float 1.0, float 2.0, float 0.5, float 4.0) - ret void -} - -; GCN-LABEL: {{^}}test_export_param31: -; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0 -; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0 -; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5 -; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0 -; GCN: exp param31 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} -; GCN: exp param31 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} -define amdgpu_kernel void @test_export_param31() #0 { - call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 63, i32 0, float 1.0, float 2.0, float 0.5, float 4.0) - call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 63, i32 0, float 1.0, float 2.0, float 0.5, float 4.0) - ret void -} - -; GCN-LABEL: {{^}}test_export_vm: -; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0 -; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0 -; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5 -; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0 -; GCN: exp mrt0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] vm{{$}} -; GCN: exp mrt0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done vm{{$}} -define amdgpu_kernel void @test_export_vm() #0 { - call void @llvm.SI.export(i32 15, i32 1, i32 0, i32 0, i32 0, float 1.0, float 2.0, float 0.5, float 4.0) - call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float 1.0, float 2.0, float 0.5, float 4.0) - ret void -} - -attributes #0 = { nounwind "ShaderType"="0" } diff --git a/llvm/test/CodeGen/AMDGPU/llvm.SI.load.dword.ll b/llvm/test/CodeGen/AMDGPU/llvm.SI.load.dword.ll index ee0a41f2210f..51f564d96909 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.SI.load.dword.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.SI.load.dword.ll @@ -34,8 +34,8 @@ main_body: %tmp22 = call i32 @llvm.SI.buffer.load.dword.i32.v2i32(<16 x i8> %tmp10, <2 x i32> zeroinitializer, i32 1234, i32 65535, i32 1, i32 1, i32 1, i32 1, i32 0) %tmp23 = bitcast i32 %tmp22 to float - call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %tmp13, float %tmp15, float %tmp17, float %tmp19) - call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %tmp21, float %tmp23, float %tmp23, float %tmp23) + call void @llvm.amdgcn.exp.f32(i32 15, i32 12, float %tmp13, float %tmp15, float %tmp17, float %tmp19, i1 false, i1 false) + call void @llvm.amdgcn.exp.f32(i32 15, i32 12, float %tmp21, float %tmp23, float %tmp23, float %tmp23, i1 true, i1 false) ret void } @@ -45,9 +45,10 @@ declare i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8>, i32, i32, i32, i32, i3 ; Function Attrs: nounwind readonly declare i32 @llvm.SI.buffer.load.dword.i32.v2i32(<16 x i8>, <2 x i32>, i32, i32, i32, i32, i32, i32, i32) #0 -declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) +declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #1 attributes #0 = { nounwind readonly } +attributes #1 = { nounwind inaccessiblememonly } !0 = !{!"const", !1, i32 1} !1 = !{!"tbaa root"}