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[X86][AVX512] Strengthen the assertions from r269001. We need VLX to use the 128/256-bit move opcodes for extended registers. 

llvm-svn: 269019
This commit is contained in:
Craig Topper 2016-05-10 05:28:04 +00:00
parent 9f8e50cdb4
commit 3e0c038a84
1 changed files with 3 additions and 2 deletions
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5
llvm/lib/Target/X86/X86InstrInfo.cpp
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@ -4653,7 +4653,7 @@ static unsigned getLoadStoreRegOpcode(unsigned Reg,
return load ? (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm)
: (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
}
assert(STI.hasAVX512() && "Using extended register requires AVX512");
assert(STI.hasVLX() && "Using extended register requires VLX");
if (isStackAligned)
return load ? X86::VMOVAPSZ128rm : X86::VMOVAPSZ128mr;
else
@ -4669,13 +4669,14 @@ static unsigned getLoadStoreRegOpcode(unsigned Reg,
else
return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
}
assert(STI.hasAVX512() && "Using extended register requires AVX512");
assert(STI.hasVLX() && "Using extended register requires VLX");
if (isStackAligned)
return load ? X86::VMOVAPSZ256rm : X86::VMOVAPSZ256mr;
else
return load ? X86::VMOVUPSZ256rm : X86::VMOVUPSZ256mr;
case 64:
assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
assert(STI.hasVLX() && "Using 512-bit register requires AVX512");
if (isStackAligned)
return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
else