[X86] Modify BypassSlowDivision tests to match their new names (NFC)
- bypass-slow-division-32.ll: tests verifying correctness of divl-to-divb bypassing - bypass-slow-division-64.ll: tests verifying correctness of divq-to-divl bypassing - bypass-slow-division-tune.ll: tests verifying that bypassing is enabled only when appropriate Differential Revision: https://reviews.llvm.org/D28551 llvm-svn: 291804
This commit is contained in:
Nikolai Bozhenov
parent
a5f1ff1afa
commit
3db8bcdbba
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@ -1,11 +1,12 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mcpu=atom -mtriple=i686-linux | FileCheck %s
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; Check that 32-bit division is bypassed correctly.
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; RUN: llc < %s -mattr=+idivl-to-divb -mtriple=i686-linux | FileCheck %s
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define i32 @Test_get_quotient(i32 %a, i32 %b) nounwind {
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; CHECK-LABEL: Test_get_quotient:
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; CHECK: # BB#0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl %eax, %edx
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; CHECK-NEXT: orl %ecx, %edx
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; CHECK-NEXT: testl $-256, %edx
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@ -27,8 +28,8 @@ define i32 @Test_get_quotient(i32 %a, i32 %b) nounwind {
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define i32 @Test_get_remainder(i32 %a, i32 %b) nounwind {
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; CHECK-LABEL: Test_get_remainder:
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; CHECK: # BB#0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl %eax, %edx
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; CHECK-NEXT: orl %ecx, %edx
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; CHECK-NEXT: testl $-256, %edx
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@ -51,8 +52,8 @@ define i32 @Test_get_remainder(i32 %a, i32 %b) nounwind {
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define i32 @Test_get_quotient_and_remainder(i32 %a, i32 %b) nounwind {
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; CHECK-LABEL: Test_get_quotient_and_remainder:
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; CHECK: # BB#0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl %eax, %edx
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; CHECK-NEXT: orl %ecx, %edx
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; CHECK-NEXT: testl $-256, %edx
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@ -82,8 +83,8 @@ define i32 @Test_use_div_and_idiv(i32 %a, i32 %b) nounwind {
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; CHECK-NEXT: pushl %ebx
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; CHECK-NEXT: pushl %edi
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; CHECK-NEXT: pushl %esi
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ebx
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: movl %ecx, %edi
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; CHECK-NEXT: orl %ebx, %edi
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; CHECK-NEXT: testl $-256, %edi
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@ -130,12 +131,6 @@ define i32 @Test_use_div_imm_imm() nounwind {
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; CHECK-LABEL: Test_use_div_imm_imm:
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; CHECK: # BB#0:
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; CHECK-NEXT: movl $64, %eax
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; CHECK-NEXT: nop
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; CHECK-NEXT: nop
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; CHECK-NEXT: nop
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; CHECK-NEXT: nop
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; CHECK-NEXT: nop
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; CHECK-NEXT: nop
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; CHECK-NEXT: retl
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%resultdiv = sdiv i32 256, 4
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ret i32 %resultdiv
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@ -147,8 +142,8 @@ define i32 @Test_use_div_reg_imm(i32 %a) nounwind {
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; CHECK-NEXT: movl $1041204193, %eax # imm = 0x3E0F83E1
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; CHECK-NEXT: imull {{[0-9]+}}(%esp)
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; CHECK-NEXT: movl %edx, %eax
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; CHECK-NEXT: sarl $3, %edx
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; CHECK-NEXT: shrl $31, %eax
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; CHECK-NEXT: sarl $3, %edx
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; CHECK-NEXT: leal (%edx,%eax), %eax
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; CHECK-NEXT: retl
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%resultdiv = sdiv i32 %a, 33
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@ -163,8 +158,8 @@ define i32 @Test_use_rem_reg_imm(i32 %a) nounwind {
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; CHECK-NEXT: movl %ecx, %eax
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; CHECK-NEXT: imull %edx
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; CHECK-NEXT: movl %edx, %eax
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; CHECK-NEXT: sarl $3, %edx
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; CHECK-NEXT: shrl $31, %eax
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; CHECK-NEXT: sarl $3, %edx
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; CHECK-NEXT: addl %eax, %edx
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; CHECK-NEXT: movl %edx, %eax
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; CHECK-NEXT: shll $5, %eax
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@ -184,8 +179,8 @@ define i32 @Test_use_divrem_reg_imm(i32 %a) nounwind {
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; CHECK-NEXT: movl %ecx, %eax
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; CHECK-NEXT: imull %edx
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; CHECK-NEXT: movl %edx, %eax
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; CHECK-NEXT: sarl $3, %edx
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; CHECK-NEXT: shrl $31, %eax
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; CHECK-NEXT: sarl $3, %edx
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; CHECK-NEXT: addl %eax, %edx
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; CHECK-NEXT: movl %edx, %eax
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; CHECK-NEXT: shll $5, %eax
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@ -1,6 +1,6 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mcpu=atom -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
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; RUN: llc < %s -mcpu=sandybridge -mtriple=x86_64-unknown-linux-gnu | FileCheck %s -check-prefix=SNB
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; Check that 64-bit division is bypassed correctly.
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; RUN: llc < %s -mattr=+idivq-to-divl -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
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; Additional tests for 64-bit divide bypass
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@ -8,8 +8,8 @@ define i64 @Test_get_quotient(i64 %a, i64 %b) nounwind {
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; CHECK-LABEL: Test_get_quotient:
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; CHECK: # BB#0:
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: movabsq $-4294967296, %rcx # imm = 0xFFFFFFFF00000000
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; CHECK-NEXT: orq %rsi, %rax
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; CHECK-NEXT: movabsq $-4294967296, %rcx # imm = 0xFFFFFFFF00000000
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; CHECK-NEXT: testq %rcx, %rax
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; CHECK-NEXT: je .LBB0_1
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; CHECK-NEXT: # BB#2:
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@ -23,25 +23,6 @@ define i64 @Test_get_quotient(i64 %a, i64 %b) nounwind {
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; CHECK-NEXT: divl %esi
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; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<def>
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; CHECK-NEXT: retq
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;
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; SNB-LABEL: Test_get_quotient:
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; SNB: # BB#0:
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; SNB-NEXT: movq %rdi, %rax
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; SNB-NEXT: orq %rsi, %rax
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; SNB-NEXT: movabsq $-4294967296, %rcx # imm = 0xFFFFFFFF00000000
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; SNB-NEXT: testq %rcx, %rax
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; SNB-NEXT: je .LBB0_1
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; SNB-NEXT: # BB#2:
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; SNB-NEXT: movq %rdi, %rax
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; SNB-NEXT: cqto
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; SNB-NEXT: idivq %rsi
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; SNB-NEXT: retq
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; SNB-NEXT: .LBB0_1:
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; SNB-NEXT: xorl %edx, %edx
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; SNB-NEXT: movl %edi, %eax
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; SNB-NEXT: divl %esi
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; SNB-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<def>
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; SNB-NEXT: retq
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%result = sdiv i64 %a, %b
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ret i64 %result
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}
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@ -50,8 +31,8 @@ define i64 @Test_get_remainder(i64 %a, i64 %b) nounwind {
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; CHECK-LABEL: Test_get_remainder:
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; CHECK: # BB#0:
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: movabsq $-4294967296, %rcx # imm = 0xFFFFFFFF00000000
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; CHECK-NEXT: orq %rsi, %rax
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; CHECK-NEXT: movabsq $-4294967296, %rcx # imm = 0xFFFFFFFF00000000
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; CHECK-NEXT: testq %rcx, %rax
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; CHECK-NEXT: je .LBB1_1
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; CHECK-NEXT: # BB#2:
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@ -67,27 +48,6 @@ define i64 @Test_get_remainder(i64 %a, i64 %b) nounwind {
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; CHECK-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<def>
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; CHECK-NEXT: movq %rdx, %rax
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; CHECK-NEXT: retq
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;
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; SNB-LABEL: Test_get_remainder:
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; SNB: # BB#0:
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; SNB-NEXT: movq %rdi, %rax
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; SNB-NEXT: orq %rsi, %rax
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; SNB-NEXT: movabsq $-4294967296, %rcx # imm = 0xFFFFFFFF00000000
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; SNB-NEXT: testq %rcx, %rax
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; SNB-NEXT: je .LBB1_1
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; SNB-NEXT: # BB#2:
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; SNB-NEXT: movq %rdi, %rax
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; SNB-NEXT: cqto
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; SNB-NEXT: idivq %rsi
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; SNB-NEXT: movq %rdx, %rax
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; SNB-NEXT: retq
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; SNB-NEXT: .LBB1_1:
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; SNB-NEXT: xorl %edx, %edx
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; SNB-NEXT: movl %edi, %eax
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; SNB-NEXT: divl %esi
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; SNB-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<def>
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; SNB-NEXT: movq %rdx, %rax
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; SNB-NEXT: retq
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%result = srem i64 %a, %b
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ret i64 %result
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}
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@ -96,8 +56,8 @@ define i64 @Test_get_quotient_and_remainder(i64 %a, i64 %b) nounwind {
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; CHECK-LABEL: Test_get_quotient_and_remainder:
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; CHECK: # BB#0:
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: movabsq $-4294967296, %rcx # imm = 0xFFFFFFFF00000000
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; CHECK-NEXT: orq %rsi, %rax
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; CHECK-NEXT: movabsq $-4294967296, %rcx # imm = 0xFFFFFFFF00000000
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; CHECK-NEXT: testq %rcx, %rax
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; CHECK-NEXT: je .LBB2_1
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; CHECK-NEXT: # BB#2:
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@ -110,32 +70,10 @@ define i64 @Test_get_quotient_and_remainder(i64 %a, i64 %b) nounwind {
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; CHECK-NEXT: xorl %edx, %edx
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: divl %esi
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; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<def>
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; CHECK-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<def>
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; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<def>
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; CHECK-NEXT: addq %rdx, %rax
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; CHECK-NEXT: retq
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;
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; SNB-LABEL: Test_get_quotient_and_remainder:
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; SNB: # BB#0:
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; SNB-NEXT: movq %rdi, %rax
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; SNB-NEXT: orq %rsi, %rax
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; SNB-NEXT: movabsq $-4294967296, %rcx # imm = 0xFFFFFFFF00000000
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; SNB-NEXT: testq %rcx, %rax
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; SNB-NEXT: je .LBB2_1
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; SNB-NEXT: # BB#2:
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; SNB-NEXT: movq %rdi, %rax
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; SNB-NEXT: cqto
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; SNB-NEXT: idivq %rsi
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; SNB-NEXT: addq %rdx, %rax
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; SNB-NEXT: retq
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; SNB-NEXT: .LBB2_1:
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; SNB-NEXT: xorl %edx, %edx
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; SNB-NEXT: movl %edi, %eax
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; SNB-NEXT: divl %esi
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; SNB-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<def>
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; SNB-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<def>
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; SNB-NEXT: addq %rdx, %rax
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; SNB-NEXT: retq
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%resultdiv = sdiv i64 %a, %b
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%resultrem = srem i64 %a, %b
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%result = add i64 %resultdiv, %resultrem
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@ -1,44 +1,56 @@
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; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=+idivl-to-divb < %s | FileCheck -check-prefix=DIV32 %s
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; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=+idivq-to-divl < %s | FileCheck -check-prefix=DIV64 %s
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; Check that a division is bypassed when appropriate only.
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; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=atom < %s | FileCheck -check-prefixes=ATOM,CHECK %s
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; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=silvermont < %s | FileCheck -check-prefixes=REST,CHECK %s
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; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=skylake < %s | FileCheck -check-prefixes=REST,CHECK %s
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; Verify that div32 is bypassed only for Atoms.
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define i32 @div32(i32 %a, i32 %b) {
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entry:
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; DIV32-LABEL: div32:
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; DIV32: orl %{{.*}}, [[REG:%[a-z]+]]
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; DIV32: testl $-256, [[REG]]
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; DIV32: divb
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; DIV64-LABEL: div32:
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; DIV64-NOT: divb
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; ATOM-LABEL: div32:
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; ATOM: orl %{{.*}}, [[REG:%[a-z]+]]
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; ATOM: testl $-256, [[REG]]
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; ATOM: divb
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;
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; REST-LABEL: div32:
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; REST-NOT: divb
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;
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%div = sdiv i32 %a, %b
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ret i32 %div
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}
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; Verify that div64 is always bypassed.
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define i64 @div64(i64 %a, i64 %b) {
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entry:
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; DIV32-LABEL: div64:
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; DIV32-NOT: divl
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; DIV64-LABEL: div64:
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; DIV64-DAG: movabsq $-4294967296, [[REGMSK:%[a-z]+]]
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; DIV64-DAG: orq %{{.*}}, [[REG:%[a-z]+]]
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; DIV64: testq [[REGMSK]], [[REG]]
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; DIV64: divl
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; CHECK-LABEL: div64:
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; CHECK-DAG: movabsq $-4294967296, [[REGMSK:%[a-z]+]]
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; CHECK-DAG: orq %{{.*}}, [[REG:%[a-z]+]]
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; CHECK: testq [[REGMSK]], [[REG]]
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; CHECK: divl
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;
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%div = sdiv i64 %a, %b
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ret i64 %div
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}
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; Verify that no extra code is generated when optimizing for size.
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define i64 @div64_optsize(i64 %a, i64 %b) optsize {
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; CHECK-LABEL: div64_optsize:
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; CHECK-NOT: divl
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%div = sdiv i64 %a, %b
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ret i64 %div
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}
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define i32 @div32_optsize(i32 %a, i32 %b) optsize {
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; DIV32-LABEL: div32_optsize:
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; DIV32-NOT: divb
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; CHECK-LABEL: div32_optsize:
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; CHECK-NOT: divb
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%div = sdiv i32 %a, %b
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ret i32 %div
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}
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define i32 @div32_minsize(i32 %a, i32 %b) minsize {
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; DIV32-LABEL: div32_minsize:
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; DIV32-NOT: divb
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; CHECK-LABEL: div32_minsize:
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; CHECK-NOT: divb
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%div = sdiv i32 %a, %b
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ret i32 %div
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}
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