[AArch64] Add support for lowering bitreverse to the rbit instruction.
Differential Revision: https://reviews.llvm.org/D28379 llvm-svn: 291575
This commit is contained in:
Chad Rosier
parent
5a4a1be690
commit
3daffbf6a8
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@ -37,12 +37,6 @@ def int_aarch64_udiv : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
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def int_aarch64_hint : Intrinsic<[], [llvm_i32_ty]>;
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//===----------------------------------------------------------------------===//
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// RBIT
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def int_aarch64_rbit : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>],
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[IntrNoMem]>;
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//===----------------------------------------------------------------------===//
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// Data Barrier Instructions
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@ -77,6 +77,11 @@ static bool UpgradeIntrinsicFunction1(Function *F, Function *&NewFn) {
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switch (Name[0]) {
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default: break;
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case 'a': {
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if (Name.startswith("aarch64.rbit")) {
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NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::bitreverse,
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F->arg_begin()->getType());
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return true;
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}
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if (Name.startswith("arm.neon.vclz")) {
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Type* args[2] = {
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F->arg_begin()->getType(),
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@ -1761,6 +1766,11 @@ void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) {
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return;
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}
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case Intrinsic::bitreverse:
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CI->replaceAllUsesWith(Builder.CreateCall(NewFn, {CI->getArgOperand(0)}));
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CI->eraseFromParent();
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return;
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case Intrinsic::ctlz:
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case Intrinsic::cttz:
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assert(CI->getNumArgOperands() == 1 &&
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@ -159,6 +159,8 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::SETCC, MVT::i64, Custom);
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setOperationAction(ISD::SETCC, MVT::f32, Custom);
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setOperationAction(ISD::SETCC, MVT::f64, Custom);
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setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
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setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
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setOperationAction(ISD::BRCOND, MVT::Other, Expand);
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setOperationAction(ISD::BR_CC, MVT::i32, Custom);
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setOperationAction(ISD::BR_CC, MVT::i64, Custom);
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@ -951,10 +951,7 @@ def : Pat<(not GPR64:$Xm), (ORNXrr XZR, GPR64:$Xm)>;
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defm CLS : OneOperandData<0b101, "cls">;
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defm CLZ : OneOperandData<0b100, "clz", ctlz>;
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defm RBIT : OneOperandData<0b000, "rbit">;
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def : Pat<(int_aarch64_rbit GPR32:$Rn), (RBITWr $Rn)>;
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def : Pat<(int_aarch64_rbit GPR64:$Rn), (RBITXr $Rn)>;
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defm RBIT : OneOperandData<0b000, "rbit", bitreverse>;
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def REV16Wr : OneWRegData<0b001, "rev16",
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UnOpFrag<(rotr (bswap node:$LHS), (i64 16))>>;
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@ -1,14 +1,18 @@
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; RUN: llc -mtriple=aarch64-eabi %s -o - | FileCheck %s
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; These tests just check that the plumbing is in place for @llvm.bitreverse. The
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; actual output is massive at the moment as llvm.bitreverse is not yet legal.
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; These tests just check that the plumbing is in place for @llvm.bitreverse.
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declare <2 x i16> @llvm.bitreverse.v2i16(<2 x i16>) readnone
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define <2 x i16> @f(<2 x i16> %a) {
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; CHECK-LABEL: f:
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; CHECK: rev32
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; CHECK: ushr
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; CHECK: fmov [[REG1:w[0-9]+]], s0
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; CHECK-DAG: rbit [[REG2:w[0-9]+]], [[REG1]]
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; CHECK-DAG: fmov s0, [[REG2]]
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; CHECK-DAG: mov [[REG3:w[0-9]+]], v0.s[1]
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; CHECK-DAG: rbit [[REG4:w[0-9]+]], [[REG3]]
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; CHECK-DAG: ins v0.s[1], [[REG4]]
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; CHECK-DAG: ushr v0.2s, v0.2s, #16
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%b = call <2 x i16> @llvm.bitreverse.v2i16(<2 x i16> %a)
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ret <2 x i16> %b
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}
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@ -17,26 +21,9 @@ declare i8 @llvm.bitreverse.i8(i8) readnone
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define i8 @g(i8 %a) {
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; CHECK-LABEL: g:
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; CHECK-DAG: rev [[RV:w.*]], w0
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; CHECK-DAG: and [[L4:w.*]], [[RV]], #0xf0f0f0f
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; CHECK-DAG: and [[H4:w.*]], [[RV]], #0xf0f0f0f0
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; CHECK-DAG: lsr [[S4:w.*]], [[H4]], #4
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; CHECK-DAG: orr [[R4:w.*]], [[S4]], [[L4]], lsl #4
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; CHECK-DAG: and [[L2:w.*]], [[R4]], #0x33333333
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; CHECK-DAG: and [[H2:w.*]], [[R4]], #0xcccccccc
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; CHECK-DAG: lsr [[S2:w.*]], [[H2]], #2
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; CHECK-DAG: orr [[R2:w.*]], [[S2]], [[L2]], lsl #2
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; CHECK-DAG: mov [[P1:w.*]], #1426063360
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; CHECK-DAG: mov [[N1:w.*]], #-1442840576
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; CHECK-DAG: and [[L1:w.*]], [[R2]], [[P1]]
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; CHECK-DAG: and [[H1:w.*]], [[R2]], [[N1]]
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; CHECK-DAG: lsr [[S1:w.*]], [[H1]], #1
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; CHECK-DAG: orr [[R1:w.*]], [[S1]], [[L1]], lsl #1
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; CHECK-DAG: lsr w0, [[R1]], #24
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; CHECK-DAG: ret
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; CHECK: rbit [[REG:w[0-9]+]], w0
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; CHECK-NEXT: lsr w0, [[REG]], #24
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; CHECK-NEXT: ret
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%b = call i8 @llvm.bitreverse.i8(i8 %a)
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ret i8 %b
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}
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@ -1,5 +1,8 @@
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; RUN: llc -mtriple=aarch64-eabi %s -o - | FileCheck %s
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; The llvm.aarch64.rbit intrinsic should be auto-upgraded to the
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; target-independent bitreverse intrinsic.
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; CHECK-LABEL: rbit32
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; CHECK: rbit w0, w0
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define i32 @rbit32(i32 %t) {
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@ -18,3 +21,22 @@ entry:
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declare i64 @llvm.aarch64.rbit.i64(i64)
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declare i32 @llvm.aarch64.rbit.i32(i32)
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; CHECK-LABEL: rbit_generic32
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; CHECK: rbit w0, w0
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define i32 @rbit_generic32(i32 %t) {
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entry:
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%rbit = call i32 @llvm.bitreverse.i32(i32 %t)
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ret i32 %rbit
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}
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; CHECK-LABEL: rbit_generic64
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; CHECK: rbit x0, x0
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define i64 @rbit_generic64(i64 %t) {
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entry:
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%rbit = call i64 @llvm.bitreverse.i64(i64 %t)
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ret i64 %rbit
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}
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declare i32 @llvm.bitreverse.i32(i32) readnone
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declare i64 @llvm.bitreverse.i64(i64) readnone
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