parent
24f0f0e28f
commit
3d527f7b61
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@ -35,6 +35,7 @@ namespace {
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MachineFunction *MF;
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MachineFunction *MF;
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const TargetMachine *TM;
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const TargetMachine *TM;
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const MRegisterInfo *RegInfo;
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const MRegisterInfo *RegInfo;
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bool *PhysRegsEverUsed;
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// StackSlotForVirtReg - Maps SSA Regs => frame index on the stack where
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// StackSlotForVirtReg - Maps SSA Regs => frame index on the stack where
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// these values are spilled
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// these values are spilled
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@ -118,8 +119,10 @@ unsigned RegAllocSimple::getFreeReg(unsigned virtualReg) {
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assert(RI+regIdx != RE && "Not enough registers!");
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assert(RI+regIdx != RE && "Not enough registers!");
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unsigned PhysReg = *(RI+regIdx);
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unsigned PhysReg = *(RI+regIdx);
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if (!RegsUsed[PhysReg])
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if (!RegsUsed[PhysReg]) {
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PhysRegsEverUsed[PhysReg] = true;
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return PhysReg;
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return PhysReg;
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}
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}
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}
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}
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}
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@ -156,19 +159,20 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
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RegsUsed.resize(RegInfo->getNumRegs());
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RegsUsed.resize(RegInfo->getNumRegs());
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// a preliminary pass that will invalidate any registers that
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// This is a preliminary pass that will invalidate any registers that are
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// are used by the instruction (including implicit uses)
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// used by the instruction (including implicit uses).
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unsigned Opcode = MI->getOpcode();
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unsigned Opcode = MI->getOpcode();
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const TargetInstrDescriptor &Desc = TM->getInstrInfo()->get(Opcode);
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const TargetInstrDescriptor &Desc = TM->getInstrInfo()->get(Opcode);
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const unsigned *Regs = Desc.ImplicitUses;
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const unsigned *Regs;
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while (*Regs)
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for (Regs = Desc.ImplicitUses; *Regs; ++Regs)
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RegsUsed[*Regs++] = true;
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RegsUsed[*Regs] = true;
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Regs = Desc.ImplicitDefs;
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for (Regs = Desc.ImplicitDefs; *Regs; ++Regs) {
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while (*Regs)
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RegsUsed[*Regs] = true;
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RegsUsed[*Regs++] = true;
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PhysRegsEverUsed[*Regs] = true;
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}
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// Loop over uses, move from memory into registers
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// Loop over uses, move from memory into registers.
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for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
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for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
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MachineOperand &op = MI->getOperand(i);
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MachineOperand &op = MI->getOperand(i);
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@ -225,6 +229,10 @@ bool RegAllocSimple::runOnMachineFunction(MachineFunction &Fn) {
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TM = &MF->getTarget();
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TM = &MF->getTarget();
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RegInfo = TM->getRegisterInfo();
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RegInfo = TM->getRegisterInfo();
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PhysRegsEverUsed = new bool[RegInfo->getNumRegs()];
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std::fill(PhysRegsEverUsed, PhysRegsEverUsed+RegInfo->getNumRegs(), false);
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Fn.setUsedPhysRegs(PhysRegsEverUsed);
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// Loop over all of the basic blocks, eliminating virtual register references
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// Loop over all of the basic blocks, eliminating virtual register references
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for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
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for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
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MBB != MBBe; ++MBB)
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MBB != MBBe; ++MBB)
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