replica
/
hanchenye-llvm-project
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Provide correct encodings for NEON vmlal. 

llvm-svn: 117131
This commit is contained in:
Owen Anderson 2010-10-22 19:05:25 +00:00
parent ff11a23ef3
commit 3d0264667f
2 changed files with 83 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
llvm/lib/Target/ARM/ARMInstrNEON.td
View File

@ -1447,11 +1447,11 @@ class N3VLMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
InstrItinClass itin, string OpcodeStr, string Dt,
ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
: N3V<op24, op23, op21_20, op11_8, 0, op4,
(outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), N3RegFrm, itin,
OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
[(set QPR:$dst, (OpNode (TyQ QPR:$src1),
(TyQ (MulOp (TyD DPR:$src2),
(TyD DPR:$src3)))))]>;
(outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
[(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
(TyQ (MulOp (TyD DPR:$Vn),
(TyD DPR:$Vm)))))]>;
class N3VLMulOpSL<bit op24, bits<2> op21_20, bits<4> op11_8,
InstrItinClass itin, string OpcodeStr, string Dt,
ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>

78
llvm/test/MC/ARM/neon-mul-accum-encoding.ll
View File

@ -87,3 +87,81 @@ define <4 x float> @vmla_4xfloat(<4 x float>* %A, <4 x float>* %B, <4 x float>*
%tmp5 = fadd <4 x float> %tmp1, %tmp4
ret <4 x float> %tmp5
}
; CHECK: vmlals_8xi8
define <8 x i16> @vmlals_8xi8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i8>* %B
%tmp3 = load <8 x i8>* %C
%tmp4 = sext <8 x i8> %tmp2 to <8 x i16>
%tmp5 = sext <8 x i8> %tmp3 to <8 x i16>
; CHECK: vmlal.s8 q8, d19, d18 @ encoding: [0xa2,0x08,0xc3,0xf2]
%tmp6 = mul <8 x i16> %tmp4, %tmp5
%tmp7 = add <8 x i16> %tmp1, %tmp6
ret <8 x i16> %tmp7
}
; CHECK: vmlals_4xi16
define <4 x i32> @vmlals_4xi16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i16>* %B
%tmp3 = load <4 x i16>* %C
%tmp4 = sext <4 x i16> %tmp2 to <4 x i32>
%tmp5 = sext <4 x i16> %tmp3 to <4 x i32>
; CHECK: vmlal.s16 q8, d19, d18 @ encoding: [0xa2,0x08,0xd3,0xf2]
%tmp6 = mul <4 x i32> %tmp4, %tmp5
%tmp7 = add <4 x i32> %tmp1, %tmp6
ret <4 x i32> %tmp7
}
; CHECK: vmlals_2xi32
define <2 x i64> @vmlals_2xi32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i32>* %B
%tmp3 = load <2 x i32>* %C
%tmp4 = sext <2 x i32> %tmp2 to <2 x i64>
%tmp5 = sext <2 x i32> %tmp3 to <2 x i64>
; CHECK: vmlal.s32 q8, d19, d18 @ encoding: [0xa2,0x08,0xe3,0xf2]
%tmp6 = mul <2 x i64> %tmp4, %tmp5
%tmp7 = add <2 x i64> %tmp1, %tmp6
ret <2 x i64> %tmp7
}
; CHECK: vmlalu_8xi8
define <8 x i16> @vmlalu_8xi8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i8>* %B
%tmp3 = load <8 x i8>* %C
%tmp4 = zext <8 x i8> %tmp2 to <8 x i16>
%tmp5 = zext <8 x i8> %tmp3 to <8 x i16>
; CHECK: vmlal.u8 q8, d19, d18 @ encoding: [0xa2,0x08,0xc3,0xf3]
%tmp6 = mul <8 x i16> %tmp4, %tmp5
%tmp7 = add <8 x i16> %tmp1, %tmp6
ret <8 x i16> %tmp7
}
; CHECK: vmlalu_4xi16
define <4 x i32> @vmlalu_4xi16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i16>* %B
%tmp3 = load <4 x i16>* %C
%tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
%tmp5 = zext <4 x i16> %tmp3 to <4 x i32>
; CHECK: vmlal.u16 q8, d19, d18 @ encoding: [0xa2,0x08,0xd3,0xf3]
%tmp6 = mul <4 x i32> %tmp4, %tmp5
%tmp7 = add <4 x i32> %tmp1, %tmp6
ret <4 x i32> %tmp7
}
; CHECK: vmlalu_2xi32
define <2 x i64> @vmlalu_2xi32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i32>* %B
%tmp3 = load <2 x i32>* %C
%tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
%tmp5 = zext <2 x i32> %tmp3 to <2 x i64>
; CHECK: vmlal.u32 q8, d19, d18 @ encoding: [0xa2,0x08,0xe3,0xf3]
%tmp6 = mul <2 x i64> %tmp4, %tmp5
%tmp7 = add <2 x i64> %tmp1, %tmp6
ret <2 x i64> %tmp7
}