parent
8637523886
commit
3b5a69cc45
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@ -240,7 +240,8 @@ void llvm::emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
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Bytes -= ThisVal;
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const MCInstrDesc &MCID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3);
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const MachineInstrBuilder MIB =
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AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg).setMIFlags(MIFlags));
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AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg)
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.setMIFlags(MIFlags));
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AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal));
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} else {
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AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
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