AMDGPU: add execfix flag to SI_ELSE
Summary: SI_ELSE is lowered into two parts: s_or_saveexec_b64 dst, src (at the start of the basic block) s_xor_b64 exec, exec, dst (at the end of the basic block) The idea is that dst contains the exec mask of the preceding IF block. It can happen that SIWholeQuadMode decides to switch from WQM to Exact mode inside the basic block that contains SI_ELSE, in which case it introduces an instruction s_and_b64 exec, exec, s[...] which masks out bits that can correspond to both the IF and the ELSE paths. So the resulting sequence must be: s_or_savexec_b64 dst, src s_and_b64 exec, exec, s[...] <-- added by SIWholeQuadMode s_and_b64 dst, dst, exec <-- added by SILowerControlFlow s_xor_b64 exec, exec, dst Whether to add the additional s_and_b64 dst, dst, exec is currently determined via the ExecModified tracking. With this change, it is instead determined by an additional flag on SI_ELSE which is set by SIWholeQuadMode. Finally: It also occured to me that an alternative approach for the long run is for SILowerControlFlow to unconditionally emit s_or_saveexec_b64 dst, src ... s_and_b64 dst, dst, exec s_xor_b64 exec, exec, dst and have a pass that detects and cleans up the "redundant AND with exec" pattern where possible. This could be useful anyway, because we also add instructions s_and_b64 vcc, exec, vcc before s_cbranch_scc (in moveToALU), and those are often redundant. I have some pending changes to how KILL is lowered that could also benefit from such a cleanup pass. In any case, this current patch could help in the short term with the whole ExecModified business. Reviewers: tstellarAMD, arsenm Subscribers: arsenm, llvm-commits, kzhuravl Differential Revision: https://reviews.llvm.org/D22846 llvm-svn: 276972
This commit is contained in:
Nicolai Haehnle
parent
1081ccf855
commit
3b572002a2
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@ -1952,8 +1952,7 @@ def SI_IF: PseudoInstSI <
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}
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def SI_ELSE : PseudoInstSI <
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(outs SReg_64:$dst), (ins SReg_64:$src, brtarget:$target),
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[(set i64:$dst, (int_amdgcn_else i64:$src, bb:$target))]> {
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(outs SReg_64:$dst), (ins SReg_64:$src, brtarget:$target, i1imm:$execfix)> {
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let Constraints = "$src = $dst";
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}
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@ -2132,6 +2131,11 @@ def SI_PC_ADD_REL_OFFSET : PseudoInstSI <
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let Predicates = [isGCN] in {
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def : Pat<
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(int_amdgcn_else i64:$src, bb:$target),
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(SI_ELSE $src, $target, 0)
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>;
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def : Pat <
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(int_AMDGPU_kilp),
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(SI_KILL 0xbf800000)
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@ -84,7 +84,7 @@ private:
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bool skipIfDead(MachineInstr &MI, MachineBasicBlock &NextBB);
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void If(MachineInstr &MI);
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void Else(MachineInstr &MI, bool ExecModified);
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void Else(MachineInstr &MI);
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void Break(MachineInstr &MI);
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void IfBreak(MachineInstr &MI);
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void ElseBreak(MachineInstr &MI);
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@ -252,7 +252,7 @@ void SILowerControlFlow::If(MachineInstr &MI) {
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MI.eraseFromParent();
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}
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void SILowerControlFlow::Else(MachineInstr &MI, bool ExecModified) {
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void SILowerControlFlow::Else(MachineInstr &MI) {
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc DL = MI.getDebugLoc();
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unsigned Dst = MI.getOperand(0).getReg();
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@ -262,7 +262,7 @@ void SILowerControlFlow::Else(MachineInstr &MI, bool ExecModified) {
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TII->get(AMDGPU::S_OR_SAVEEXEC_B64), Dst)
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.addReg(Src); // Saved EXEC
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if (ExecModified) {
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if (MI.getOperand(3).getImm() != 0) {
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// Adjust the saved exec to account for the modifications during the flow
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// block that contains the ELSE. This can happen when WQM mode is switched
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// off.
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@ -427,7 +427,6 @@ bool SILowerControlFlow::runOnMachineFunction(MachineFunction &MF) {
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MachineBasicBlock *EmptyMBBAtEnd = nullptr;
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MachineBasicBlock::iterator I, Next;
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bool ExecModified = false;
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for (I = MBB.begin(); I != MBB.end(); I = Next) {
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Next = std::next(I);
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@ -438,9 +437,6 @@ bool SILowerControlFlow::runOnMachineFunction(MachineFunction &MF) {
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if (TII->isFLAT(MI))
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NeedFlat = true;
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if (I->modifiesRegister(AMDGPU::EXEC, TRI))
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ExecModified = true;
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switch (MI.getOpcode()) {
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default: break;
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case AMDGPU::SI_IF:
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@ -449,7 +445,7 @@ bool SILowerControlFlow::runOnMachineFunction(MachineFunction &MF) {
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break;
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case AMDGPU::SI_ELSE:
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Else(MI, ExecModified);
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Else(MI);
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break;
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case AMDGPU::SI_BREAK:
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@ -434,6 +434,9 @@ void SIWholeQuadMode::processBlock(MachineBasicBlock &MBB, unsigned LiveMaskReg,
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State = Needs;
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}
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if (MI.getOpcode() == AMDGPU::SI_ELSE && State == StateExact)
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MI.getOperand(3).setImm(1);
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}
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if ((BI.OutNeeds & StateWQM) && State != StateWQM) {
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@ -0,0 +1,58 @@
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; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s
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; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
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; CHECK-LABEL: {{^}}else_no_execfix:
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; CHECK: ; %Flow
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; CHECK-NEXT: s_or_saveexec_b64 [[DST:s\[[0-9]+:[0-9]+\]]],
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; CHECK-NEXT: s_xor_b64 exec, exec, [[DST]]
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; CHECK-NEXT: ; mask branch
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define amdgpu_ps float @else_no_execfix(i32 %z, float %v) {
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main_body:
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%cc = icmp sgt i32 %z, 5
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br i1 %cc, label %if, label %else
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if:
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%v.if = fmul float %v, 2.0
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br label %end
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else:
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%v.else = fmul float %v, 3.0
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br label %end
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end:
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%r = phi float [ %v.if, %if ], [ %v.else, %else ]
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ret float %r
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}
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; CHECK-LABEL: {{^}}else_execfix_leave_wqm:
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; CHECK: ; %Flow
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; CHECK-NEXT: s_or_saveexec_b64 [[DST:s\[[0-9]+:[0-9]+\]]],
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; CHECK-NEXT: s_and_b64 exec, exec,
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; CHECK-NEXT: s_and_b64 [[DST]], exec, [[DST]]
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; CHECK-NEXT: s_xor_b64 exec, exec, [[DST]]
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; CHECK-NEXT: ; mask branch
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define amdgpu_ps void @else_execfix_leave_wqm(i32 %z, float %v) {
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main_body:
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%cc = icmp sgt i32 %z, 5
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br i1 %cc, label %if, label %else
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if:
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%v.if = fmul float %v, 2.0
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br label %end
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else:
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%c = fmul float %v, 3.0
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%c.i = bitcast float %c to i32
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%tex = call <4 x float> @llvm.SI.image.sample.i32(i32 %c.i, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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%v.else = extractelement <4 x float> %tex, i32 0
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br label %end
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end:
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%r = phi float [ %v.if, %if ], [ %v.else, %else ]
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call void @llvm.amdgcn.buffer.store.f32(float %r, <4 x i32> undef, i32 0, i32 0, i1 0, i1 0)
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ret void
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}
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declare void @llvm.amdgcn.buffer.store.f32(float, <4 x i32>, i32, i32, i1, i1) nounwind
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declare <4 x float> @llvm.SI.image.sample.i32(i32, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) nounwind readnone
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