diff --git a/llvm/test/CodeGen/X86/coalescer-subreg.ll b/llvm/test/CodeGen/X86/coalescer-subreg.ll
new file mode 100644
index 000000000000..be80dff779c9
--- /dev/null
+++ b/llvm/test/CodeGen/X86/coalescer-subreg.ll
@@ -0,0 +1,29 @@
+; RUN: llc -o - %s -verify-machineinstrs
+; This used to crash when coalescing a regclass like GR16 which did not support
+; the sub_8bit_hi subregister with a class like GR16_ABCD that did.
+target triple = "x86_64-apple-macosx10.10.0"
+
+define void @test() #0 {
+entry:
+  br i1 undef, label %loop, label %for.end597
+
+loop:
+  %0 = load i16, i16* null, align 4
+  %1 = load i16, i16* undef, align 4
+  %or1 = or i16 %1, %0
+  %or2 = trunc i16 %or1 to i8
+  store i8 %or2, i8* undef, align 4
+  %2 = or i16 %1, %0
+  %or3 = lshr i16 %2, 8
+  %or4 = trunc i16 %or3 to i8
+  store i8 %or4, i8* undef, align 1
+  %3 = load i32, i32* undef, align 4
+  %4 = load i32, i32* undef, align 4
+  %or5 = or i32 %4, %3
+  store i32 %or5, i32* undef, align 4
+  store i32 0, i32* undef, align 4
+  br label %loop
+
+for.end597:
+  ret void
+}
diff --git a/llvm/utils/TableGen/CodeGenRegisters.cpp b/llvm/utils/TableGen/CodeGenRegisters.cpp
index 56ac6e0884e1..cd4075b0e759 100644
--- a/llvm/utils/TableGen/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/CodeGenRegisters.cpp
@@ -1260,7 +1260,7 @@ void CodeGenRegBank::computeSubRegLaneMasks() {
   for (auto &RegClass : RegClasses) {
     unsigned LaneMask = 0;
     for (const auto &SubRegIndex : SubRegIndices) {
-      if (RegClass.getSubClassWithSubReg(&SubRegIndex) != &RegClass)
+      if (RegClass.getSubClassWithSubReg(&SubRegIndex) == nullptr)
         continue;
       LaneMask |= SubRegIndex.LaneMask;
     }