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[CodeGen] Unify the syntax of MBB successors in MIR and -debug output 

Instead of:

Successors according to CFG: %bb.6(0x12492492 / 0x80000000 = 14.29%)

print:

successors: %bb.6(0x12492492); %bb.6(14.29%)
llvm-svn: 324685
This commit is contained in:
Francis Visoiu Mistrih 2018-02-09 00:10:31 +00:00
parent d42b1c0534
commit 39ec2e95ae
16 changed files with 65 additions and 52 deletions
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35
llvm/lib/CodeGen/MachineBasicBlock.cpp
View File

@ -333,6 +333,30 @@ void MachineBasicBlock::print(raw_ostream &OS, ModuleSlotTracker &MST,
}
OS << '\n';
}
// Print the successors
OS.indent(2) << "successors: ";
for (auto I = succ_begin(), E = succ_end(); I != E; ++I) {
if (I != succ_begin())
OS << ", ";
OS << printMBBReference(**I);
OS << '(' << format("0x%08" PRIx32, getSuccProbability(I).getNumerator())
<< ')';
}
// Print human readable probabilities as comments.
OS << "; ";
for (auto I = succ_begin(), E = succ_end(); I != E; ++I) {
const BranchProbability &BP = *getProbabilityIterator(I);
if (I != succ_begin())
OS << ", ";
OS << printMBBReference(**I) << '('
<< format("%.2f%%",
rint(((double)BP.getNumerator() / BP.getDenominator()) *
100.0 * 100.0) /
100.0)
<< ')';
}
// Print the preds of this block according to the CFG.
if (!pred_empty()) {
if (Indexes) OS << '\t';
@ -355,17 +379,6 @@ void MachineBasicBlock::print(raw_ostream &OS, ModuleSlotTracker &MST,
OS << '\n';
}
// Print the successors of this block according to the CFG.
if (!succ_empty()) {
if (Indexes) OS << '\t';
OS << " Successors according to CFG:";
for (const_succ_iterator SI = succ_begin(), E = succ_end(); SI != E; ++SI) {
OS << " " << printMBBReference(*(*SI));
if (!Probs.empty())
OS << '(' << *getProbabilityIterator(SI) << ')';
}
OS << '\n';
}
if (IrrLoopHeaderWeight) {
if (Indexes) OS << '\t';
OS << " Irreducible loop header weight: "

12
llvm/test/CodeGen/ARM/Windows/dbzchk.ll
View File

@ -33,11 +33,11 @@ return:
}
; CHECK-DIV-DAG: %bb.0
; CHECK-DIV-DAG: Successors according to CFG: %bb.1({{.*}}) %bb.2
; CHECK-DIV-DAG: successors: %bb.1({{.*}}), %bb.2
; CHECK-DIV-DAG: %bb.1
; CHECK-DIV-DAG: Successors according to CFG: %bb.3
; CHECK-DIV-DAG: successors: %bb.3
; CHECK-DIV-DAG: %bb.2
; CHECK-DIV-DAG: Successors according to CFG: %bb.3
; CHECK-DIV-DAG: successors: %bb.3
; CHECK-DIV-DAG: %bb.3
; RUN: llc -mtriple thumbv7--windows-itanium -print-machineinstrs=expand-isel-pseudos -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-MOD
@ -67,11 +67,11 @@ return:
}
; CHECK-MOD-DAG: %bb.0
; CHECK-MOD-DAG: Successors according to CFG: %bb.2({{.*}}) %bb.1
; CHECK-MOD-DAG: successors: %bb.2({{.*}}), %bb.1
; CHECK-MOD-DAG: %bb.1
; CHECK-MOD-DAG: Successors according to CFG: %bb.3
; CHECK-MOD-DAG: successors: %bb.3
; CHECK-MOD-DAG: %bb.3
; CHECK-MOD-DAG: Successors according to CFG: %bb.2
; CHECK-MOD-DAG: successors: %bb.2
; CHECK-MOD-DAG: %bb.2
; RUN: llc -mtriple thumbv7--windows-itanium -print-machineinstrs=expand-isel-pseudos -verify-machineinstrs -filetype asm -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-CFG

2
llvm/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll
View File

@ -22,7 +22,7 @@ entry:
; for.body -> for.cond.backedge (100%)
; -> cond.false.i (0%)
; CHECK: bb.1.for.body:
; CHECK: Successors according to CFG: %bb.2(0x80000000 / 0x80000000 = 100.00%) %bb.4(0x00000001 / 0x80000000 = 0.00%)
; CHECK: successors: %bb.2(0x80000000), %bb.4(0x00000001)
for.body:
br i1 undef, label %for.cond.backedge, label %lor.lhs.false.i, !prof !1

2
llvm/test/CodeGen/ARM/ifcvt-branch-weight.ll
View File

@ -19,7 +19,7 @@ bb:
br i1 %9, label %return, label %bb2
; CHECK: bb.2.bb2:
; CHECK: Successors according to CFG: %bb.4({{[0-9a-fx/= ]+}}50.00%) %bb.3({{[0-9a-fx/= ]+}}50.00%)
; CHECK: successors: %bb.4(0x40000000), %bb.3(0x40000000)
bb2:
%v10 = icmp eq i32 %3, 16

4
llvm/test/CodeGen/ARM/ifcvt-iter-indbr.ll
View File

@ -31,9 +31,9 @@ declare i8* @bar(i32, i8*, i8*)
; CHECK-NEXT: bl _foo
;
; CHECK-PROB: bb.0{{[0-9a-zA-Z.]*}}:
; CHECK-PROB: Successors according to CFG: %bb.1({{[0-9a-fx/= ]+}}50.00%) %bb.3({{[0-9a-fx/= ]+}}25.00%) %bb.5({{[0-9a-fx/= ]+}}25.00%)
; CHECK-PROB: successors: %bb.1(0x40000000), %bb.3(0x20000000), %bb.5(0x20000000)
; CHECK-PROB: bb.2{{[0-9a-zA-Z.]*}}:
; CHECK-PROB: Successors according to CFG: %bb.3({{[0-9a-fx/= ]+}}50.00%) %bb.5({{[0-9a-fx/= ]+}}50.00%)
; CHECK-PROB: successors: %bb.3(0x40000000), %bb.5(0x40000000)
define i32 @test(i32 %a, i32 %a2, i32* %p, i32* %p2) "no-frame-pointer-elim"="true" {
entry:

2
llvm/test/CodeGen/ARM/tail-merge-branch-weight.ll
View File

@ -9,7 +9,7 @@
; = 0.2 * 0.4 + 0.8 * 0.7 = 0.64
; CHECK: # Machine code for function test0:
; CHECK: Successors according to CFG: %bb.{{[0-9]+}}({{[0-9a-fx/= ]+}}20.00%) %bb.{{[0-9]+}}({{[0-9a-fx/= ]+}}80.00%)
; CHECK: successors: %bb.{{[0-9]+}}(0x1999999a), %bb.{{[0-9]+}}(0x66666666)
; CHECK: bb.{{[0-9]+}}{{[0-9a-zA-Z.]*}}:
; CHECK: bb.{{[0-9]+}}{{[0-9a-zA-Z.]*}}:
; CHECK: # End machine code for function test0.

4
llvm/test/CodeGen/ARM/taildup-branch-weight.ll
View File

@ -3,7 +3,7 @@
; RUN: | FileCheck %s
; CHECK: Machine code for function test0:
; CHECK: Successors according to CFG: %bb.1({{[0-9a-fx/= ]+}}3.12%) %bb.2({{[0-9a-fx/= ]+}}96.88%)
; CHECK: successors: %bb.1(0x04000000), %bb.2(0x7c000000)
define void @test0(i32 %a, i32 %b, i32* %c, i32* %d) {
entry:
@ -30,7 +30,7 @@ B4:
!0 = !{!"branch_weights", i32 4, i32 124}
; CHECK: Machine code for function test1:
; CHECK: Successors according to CFG: %bb.2(0x7c000000 / 0x80000000 = 96.88%) %bb.1(0x04000000 / 0x80000000 = 3.12%)
; CHECK: successors: %bb.2(0x7c000000), %bb.1(0x04000000)
@g0 = common global i32 0, align 4

4
llvm/test/CodeGen/AVR/select-must-add-unconditional-jump.ll
View File

@ -10,13 +10,13 @@
; This issue manifests in a CFG that looks something like this:
;
; %bb.2.finish:
; successors: %bb.5(?%) %bb.6(?%)
; Predecessors according to CFG: %bb.0 %bb.1
; %0 = PHI %3, <%bb.0>, %5, <%bb.1>
; %7 = LDIRdK 2
; %8 = LDIRdK 1
; CPRdRr %2, %0, implicit-def %SREG
; BREQk <%bb.6>, implicit %SREG
; Successors according to CFG: %bb.5(?%) %bb.6(?%)
;
; The code assumes it the fallthrough block after this is %bb.5, but
; it's actually %bb.3! To be proper, there should be an unconditional
@ -50,9 +50,9 @@ dead:
; both successors.
; CHECK: bb.2.finish:
; CHECK: successors:
; CHECK: BREQk [[BRANCHED:%bb.[0-9]+]]
; CHECK: RJMPk [[DIRECT:%bb.[0-9]+]]
; CHECK: Successors according to CFG
; CHECK-SAME-DAG: {{.*}}[[BRANCHED]]
; CHECK-SAME-DAG: {{.*}}[[DIRECT]]
; CHECK: bb.3.dead:

10
llvm/test/CodeGen/Generic/MachineBranchProb.ll
View File

@ -22,13 +22,13 @@ entry:
i64 15, label %sw.bb
], !prof !0
; CHECK: bb.0.entry:
; CHECK: Successors according to CFG: %bb.1({{[0-9a-fx/= ]+}}92.17%) %bb.4({{[0-9a-fx/= ]+}}7.83%)
; CHECK: successors: %bb.1(0x75f8ebf2), %bb.4(0x0a07140e)
; CHECK: bb.4.entry:
; CHECK: Successors according to CFG: %bb.2({{[0-9a-fx/= ]+}}75.29%) %bb.5({{[0-9a-fx/= ]+}}24.71%)
; CHECK: successors: %bb.2(0x60606068), %bb.5(0x1f9f9f98)
; CHECK: bb.5.entry:
; CHECK: Successors according to CFG: %bb.1({{[0-9a-fx/= ]+}}47.62%) %bb.6({{[0-9a-fx/= ]+}}52.38%)
; CHECK: successors: %bb.1(0x3cf3cf4b), %bb.6(0x430c30b5)
; CHECK: bb.6.entry:
; CHECK: Successors according to CFG: %bb.1({{[0-9a-fx/= ]+}}36.36%) %bb.3({{[0-9a-fx/= ]+}}63.64%)
; CHECK: successors: %bb.1(0x2e8ba2d7), %bb.3(0x51745d29)
sw.bb:
; this call will prevent simplifyCFG from optimizing the block away in ARM/AArch64.
@ -72,7 +72,7 @@ return: ret void
; CHECK-LABEL: Machine code for function left_leaning_weight_balanced_tree:
; CHECK: bb.0.entry:
; CHECK-NOT: Successors
; CHECK: Successors according to CFG: %bb.8({{[0-9a-fx/= ]+}}39.71%) %bb.9({{[0-9a-fx/= ]+}}60.29%)
; CHECK: successors: %bb.8(0x32d2d2d3), %bb.9(0x4d2d2d2d)
}
!1 = !{!"branch_weights",

2
llvm/test/CodeGen/Hexagon/ifcvt-edge-weight.ll
View File

@ -2,7 +2,7 @@
; Check that the edge weights are updated correctly after if-conversion.
; CHECK: bb.3.if{{[0-9a-zA-Z.]*}}:
; CHECK: Successors according to CFG: %bb.2({{[0-9a-fx/= ]+}}10.00%) %bb.1({{[0-9a-fx/= ]+}}90.00%)
; CHECK: successors: %bb.2(0x0ccccccd), %bb.1(0x73333333)
@a = external global i32
@d = external global i32

4
llvm/test/CodeGen/X86/2010-05-12-FastAllocKills.ll
View File

@ -4,16 +4,17 @@ target triple = "x86_64-apple-darwin"
; This test causes a virtual FP register to be redefined while it is live:
;%bb.5.bb10:
; successors: %bb.5
; Predecessors according to CFG: %bb.4 %bb.5
; %reg1024 = MOV_Fp8080 %reg1034
; %reg1025 = MUL_Fp80m32 %reg1024, %rip, 1, %reg0, %const.0, %reg0; mem:LD4[ConstantPool]
; %reg1034 = MOV_Fp8080 %reg1025
; FP_REG_KILL implicit-def %fp0, implicit-def %fp1, implicit-def %fp2, implicit-def %fp3, implicit-def %fp4, implicit-def %fp5, implicit-def %fp6
; JMP_4 <%bb.5>
; Successors according to CFG: %bb.5
;
; The X86FP pass needs good kill flags, like on %fp0 representing %reg1034:
;%bb.5.bb10:
; successors: %bb.5
; Predecessors according to CFG: %bb.4 %bb.5
; %fp0 = LD_Fp80m %stack.3, 1, %reg0, 0, %reg0; mem:LD10[FixedStack3](align=4)
; %fp1 = MOV_Fp8080 killed %fp0
@ -24,7 +25,6 @@ target triple = "x86_64-apple-darwin"
; ST_FpP80m %stack.5, 1, %reg0, 0, %reg0, killed %fp2; mem:ST10[FixedStack5](align=4)
; FP_REG_KILL implicit-def %fp0, implicit-def %fp1, implicit-def %fp2, implicit-def %fp3, implicit-def %fp4, implicit-def %fp5, implicit-def %fp6
; JMP_4 <%bb.5>
; Successors according to CFG: %bb.5
define fastcc i32 @sqlite3AtoF(i8* %z, double* nocapture %pResult) nounwind ssp {
entry:

4
llvm/test/CodeGen/X86/MachineBranchProb.ll
View File

@ -18,9 +18,9 @@ for.cond2: ; preds = %for.inc, %for.cond
%or.cond = or i1 %tobool, %cmp4
br i1 %or.cond, label %for.inc20, label %for.inc, !prof !0
; CHECK: bb.1.for.cond2:
; CHECK: Successors according to CFG: %bb.3({{[0-9a-fx/= ]+}}1.53%) %bb.4({{[0-9a-fx/= ]+}}98.47%)
; CHECK: successors: %bb.3(0x01f3d4c5), %bb.4(0x7e0c2b3b)
; CHECK: bb.4.for.cond2:
; CHECK: Successors according to CFG: %bb.3({{[0-9a-fx/= ]+}}1.55%) %bb.2({{[0-9a-fx/= ]+}}98.45%)
; CHECK: successors: %bb.3(0x01fb92cf), %bb.2(0x7e046d31)
for.inc: ; preds = %for.cond2
%shl = shl i32 %bit.0, 1

2
llvm/test/CodeGen/X86/catchpad-weight.ll
View File

@ -2,7 +2,7 @@
; Check if the edge weight to the catchpad is calculated correctly.
; CHECK: Successors according to CFG: %bb.2(0x7ffff100 / 0x80000000 = 100.00%) %bb.1(0x00000800 / 0x80000000 = 0.00%) %bb.3(0x00000400 / 0x80000000 = 0.00%) %bb.4(0x00000200 / 0x80000000 = 0.00%) %bb.5(0x00000100 / 0x80000000 = 0.00%)
; CHECK: successors: %bb.2(0x7ffff100), %bb.1(0x00000800), %bb.3(0x00000400), %bb.4(0x00000200), %bb.5(0x00000100)
target datalayout = "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64--windows-msvc18.0.0"

4
llvm/test/CodeGen/X86/stack-protector-weight.ll
View File

@ -4,13 +4,13 @@
; RUN: llc -mtriple=i386-pc-windows-msvc -print-machineinstrs=expand-isel-pseudos -enable-selectiondag-sp=false %s -o /dev/null 2>&1 | FileCheck %s -check-prefix=MSVC-IR
; DARWIN-SELDAG: # Machine code for function test_branch_weights:
; DARWIN-SELDAG: Successors according to CFG: %bb.[[SUCCESS:[0-9]+]]({{[0-9a-fx/= ]+}}100.00%) %bb.[[FAILURE:[0-9]+]]
; DARWIN-SELDAG: successors: %bb.[[SUCCESS:[0-9]+]](0x7ffff800), %bb.[[FAILURE:[0-9]+]]
; DARWIN-SELDAG: bb.[[FAILURE]]{{[0-9a-zA-Z_.]+}}:
; DARWIN-SELDAG: CALL64pcrel32 &__stack_chk_fail
; DARWIN-SELDAG: bb.[[SUCCESS]]{{[0-9a-zA-Z_.]+}}:
; DARWIN-IR: # Machine code for function test_branch_weights:
; DARWIN-IR: Successors according to CFG: %bb.[[SUCCESS:[0-9]+]]({{[0-9a-fx/= ]+}}100.00%) %bb.[[FAILURE:[0-9]+]]
; DARWIN-IR: successors: %bb.[[SUCCESS:[0-9]+]](0x7fffffff), %bb.[[FAILURE:[0-9]+]]
; DARWIN-IR: bb.[[SUCCESS]]{{[0-9a-zA-Z_.]+}}:
; DARWIN-IR: bb.[[FAILURE]]{{[0-9a-zA-Z_.]+}}:
; DARWIN-IR: CALL64pcrel32 @__stack_chk_fail

22
llvm/test/CodeGen/X86/switch-edge-weight.ll
View File

@ -34,22 +34,22 @@ sw.epilog:
; CHECK: bb.0{{[0-9a-zA-Z.]*}}:
; %bb.0 to %bb.4: [0, 1133] (65 = 60 + 5)
; %bb.0 to %bb.5: [1134, UINT32_MAX] (25 = 20 + 5)
; CHECK: Successors according to CFG: %bb.4({{[0-9a-fx/= ]+}}72.22%) %bb.5({{[0-9a-fx/= ]+}}27.78%)
; CHECK: successors: %bb.4(0x5c71c71c), %bb.5(0x238e38e4)
;
; CHECK: bb.4{{[0-9a-zA-Z.]*}}:
; %bb.4 to %bb.1: [155, 159] (50)
; %bb.4 to %bb.5: [0, 1133] - [155, 159] (15 = 10 + 5)
; CHECK: Successors according to CFG: %bb.1({{[0-9a-fx/= ]+}}76.92%) %bb.7({{[0-9a-fx/= ]+}}23.08%)
; CHECK: successors: %bb.1(0x62762762), %bb.7(0x1d89d89e)
;
; CHECK: bb.5{{[0-9a-zA-Z.]*}}:
; %bb.5 to %bb.1: {1140} (10)
; %bb.5 to %bb.6: [1134, UINT32_MAX] - {1140} (15 = 10 + 5)
; CHECK: Successors according to CFG: %bb.1({{[0-9a-fx/= ]+}}40.00%) %bb.6({{[0-9a-fx/= ]+}}60.00%)
; CHECK: successors: %bb.1(0x33333333), %bb.6(0x4ccccccd)
;
; CHECK: bb.6{{[0-9a-zA-Z.]*}}:
; %bb.6 to %bb.1: {1134} (10)
; %bb.6 to %bb.2: [1134, UINT32_MAX] - {1134, 1140} (5)
; CHECK: Successors according to CFG: %bb.1({{[0-9a-fx/= ]+}}66.67%) %bb.2({{[0-9a-fx/= ]+}}33.33%)
; CHECK: successors: %bb.1(0x55555555), %bb.2(0x2aaaaaab)
}
; CHECK-LABEL: test2
@ -102,7 +102,7 @@ sw.epilog:
; CHECK: bb.0{{[0-9a-zA-Z.]*}}:
; %bb.0 to %bb.6: {0} + [15, UINT32_MAX] (5)
; %bb.0 to %bb.8: [1, 14] (jump table) (65 = 60 + 5)
; CHECK: Successors according to CFG: %bb.6({{[0-9a-fx/= ]+}}7.14%) %bb.8({{[0-9a-fx/= ]+}}92.86%
; CHECK: successors: %bb.6(0x09249249), %bb.8(0x76db6db7)
;
; CHECK: bb.8{{[0-9a-zA-Z.]*}}:
; %bb.8 to %bb.1: {1} (10)
@ -111,7 +111,7 @@ sw.epilog:
; %bb.8 to %bb.3: {11} (10)
; %bb.8 to %bb.4: {12} (10)
; %bb.8 to %bb.5: {13, 14} (20)
; CHECK: Successors according to CFG: %bb.1({{[0-9a-fx/= ]+}}15.38%) %bb.6({{[0-9a-fx/= ]+}}7.69%) %bb.2({{[0-9a-fx/= ]+}}15.38%) %bb.3({{[0-9a-fx/= ]+}}15.38%) %bb.4({{[0-9a-fx/= ]+}}15.38%) %bb.5({{[0-9a-fx/= ]+}}30.77%)
; CHECK: successors: %bb.1(0x13b13b14), %bb.6(0x09d89d8a), %bb.2(0x13b13b14), %bb.3(0x13b13b14), %bb.4(0x13b13b14), %bb.5(0x27627628)
}
; CHECK-LABEL: test3
@ -163,7 +163,7 @@ sw.epilog:
; CHECK: bb.0{{[0-9a-zA-Z.]*}}:
; %bb.0 to %bb.6: [0, 9] + [15, UINT32_MAX] {10}
; %bb.0 to %bb.8: [10, 14] (jump table) (50)
; CHECK: Successors according to CFG: %bb.6({{[0-9a-fx/= ]+}}16.67%) %bb.8({{[0-9a-fx/= ]+}}83.33%)
; CHECK: successors: %bb.6(0x15555555), %bb.8(0x6aaaaaab)
;
; CHECK: bb.8{{[0-9a-zA-Z.]*}}:
; %bb.8 to %bb.1: {10} (10)
@ -171,7 +171,7 @@ sw.epilog:
; %bb.8 to %bb.3: {12} (10)
; %bb.8 to %bb.4: {13} (10)
; %bb.8 to %bb.5: {14} (10)
; CHECK: Successors according to CFG: %bb.1({{[0-9a-fx/= ]+}}20.00%) %bb.2({{[0-9a-fx/= ]+}}20.00%) %bb.3({{[0-9a-fx/= ]+}}20.00%) %bb.4({{[0-9a-fx/= ]+}}20.00%) %bb.5({{[0-9a-fx/= ]+}}20.00%)
; CHECK: successors: %bb.1(0x1999999a), %bb.2(0x1999999a), %bb.3(0x1999999a), %bb.4(0x1999999a), %bb.5(0x1999999a)
}
; CHECK-LABEL: test4
@ -216,12 +216,12 @@ sw.epilog:
; CHECK: bb.0{{[0-9a-zA-Z.]*}}:
; %bb.0 to %bb.6: [0, 110] + [116, UINT32_MAX] (20)
; %bb.0 to %bb.7: [111, 115] (bit test) (50)
; CHECK: Successors according to CFG: %bb.6({{[0-9a-fx/= ]+}}28.57%) %bb.7({{[0-9a-fx/= ]+}}71.43%)
; CHECK: successors: %bb.6(0x24924925), %bb.7(0x5b6db6db)
;
; CHECK: bb.7{{[0-9a-zA-Z.]*}}:
; %bb.7 to %bb.2: {111, 114, 115} (30)
; %bb.7 to %bb.3: {112, 113} (20)
; CHECK: Successors according to CFG: %bb.2({{[0-9a-fx/= ]+}}60.00%) %bb.3({{[0-9a-fx/= ]+}}40.00%)
; CHECK: successors: %bb.2(0x4ccccccd), %bb.3(0x33333333)
}
; CHECK-LABEL: test5
@ -273,7 +273,7 @@ sw.epilog:
; CHECK: bb.0{{[0-9a-zA-Z.]*}}:
; %bb.0 to %bb.6: [10, UINT32_MAX] (15)
; %bb.0 to %bb.8: [4, 20, 28, 36] (jump table) (45)
; CHECK: Successors according to CFG: %bb.8({{[0-9a-fx/= ]+}}25.00%) %bb.9({{[0-9a-fx/= ]+}}75.00%)
; CHECK: successors: %bb.8(0x20000001), %bb.9(0x5fffffff)
}
!1 = !{!"branch_weights", i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10}

4
llvm/test/CodeGen/X86/switch-jump-table.ll
View File

@ -55,8 +55,8 @@ default:
define void @bar(i32 %x, i32* %to) {
; CHECK-JT-PROB-LABEL: bar:
; CHECK-JT-PROB: Successors according to CFG: %bb.6({{[0-9a-fx/= ]+}}14.29%) %bb.8({{[0-9a-fx/= ]+}}85.71%)
; CHECK-JT-PROB: Successors according to CFG: %bb.1({{[0-9a-fx/= ]+}}16.67%) %bb.2({{[0-9a-fx/= ]+}}16.67%) %bb.3({{[0-9a-fx/= ]+}}16.67%) %bb.4({{[0-9a-fx/= ]+}}16.67%) %bb.5({{[0-9a-fx/= ]+}}33.33%)
; CHECK-JT-PROB: successors: %bb.6(0x12492492), %bb.8(0x6db6db6e)
; CHECK-JT-PROB: successors: %bb.1(0x15555555), %bb.2(0x15555555), %bb.3(0x15555555), %bb.4(0x15555555), %bb.5(0x2aaaaaab)
entry:
switch i32 %x, label %default [