[X86] Add immediate range checks for many of the builtins.
This time allow -128 to 255 for builtins that use a char type immediate." llvm-svn: 269878
This commit is contained in:
Craig Topper
parent
16ff860469
commit
39c871038a
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@ -368,7 +368,7 @@ TARGET_BUILTIN(__builtin_ia32_monitor, "vv*UiUi", "", "sse3")
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TARGET_BUILTIN(__builtin_ia32_mwait, "vUiUi", "", "sse3")
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TARGET_BUILTIN(__builtin_ia32_lddqu, "V16ccC*", "", "sse3")
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TARGET_BUILTIN(__builtin_ia32_palignr128, "V16cV16cV16cIc", "", "ssse3")
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TARGET_BUILTIN(__builtin_ia32_palignr128, "V16cV16cV16cIi", "", "ssse3")
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TARGET_BUILTIN(__builtin_ia32_insertps128, "V4fV4fV4fIc", "", "sse4.1")
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TARGET_BUILTIN(__builtin_ia32_pblendvb128, "V16cV16cV16cV16c", "", "sse4.1")
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@ -537,7 +537,7 @@ TARGET_BUILTIN(__builtin_ia32_paddusb256, "V32cV32cV32c", "", "avx2")
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TARGET_BUILTIN(__builtin_ia32_paddusw256, "V16sV16sV16s", "", "avx2")
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TARGET_BUILTIN(__builtin_ia32_psubusb256, "V32cV32cV32c", "", "avx2")
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TARGET_BUILTIN(__builtin_ia32_psubusw256, "V16sV16sV16s", "", "avx2")
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TARGET_BUILTIN(__builtin_ia32_palignr256, "V32cV32cV32cIc", "", "avx2")
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TARGET_BUILTIN(__builtin_ia32_palignr256, "V32cV32cV32cIi", "", "avx2")
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TARGET_BUILTIN(__builtin_ia32_pavgb256, "V32cV32cV32c", "", "avx2")
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TARGET_BUILTIN(__builtin_ia32_pavgw256, "V16sV16sV16s", "", "avx2")
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TARGET_BUILTIN(__builtin_ia32_pblendvb256, "V32cV32cV32cV32c", "", "avx2")
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@ -1315,7 +1315,7 @@ static bool SemaBuiltinCpuSupports(Sema &S, CallExpr *TheCall) {
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}
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bool Sema::CheckX86BuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) {
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unsigned i = 0, l = 0, u = 0;
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int i = 0, l = 0, u = 0;
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switch (BuiltinID) {
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default:
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return false;
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@ -1323,23 +1323,52 @@ bool Sema::CheckX86BuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) {
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return SemaBuiltinCpuSupports(*this, TheCall);
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case X86::BI__builtin_ms_va_start:
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return SemaBuiltinMSVAStart(TheCall);
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case X86::BI__builtin_ia32_extractf64x4_mask:
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case X86::BI__builtin_ia32_extracti64x4_mask:
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case X86::BI__builtin_ia32_extractf32x8_mask:
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case X86::BI__builtin_ia32_extracti32x8_mask:
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case X86::BI__builtin_ia32_extractf64x2_256_mask:
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case X86::BI__builtin_ia32_extracti64x2_256_mask:
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case X86::BI__builtin_ia32_extractf32x4_256_mask:
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case X86::BI__builtin_ia32_extracti32x4_256_mask:
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i = 1; l = 0; u = 1;
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break;
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case X86::BI_mm_prefetch:
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i = 1;
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l = 0;
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u = 3;
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case X86::BI__builtin_ia32_extractf32x4_mask:
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case X86::BI__builtin_ia32_extracti32x4_mask:
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case X86::BI__builtin_ia32_vpermilpd_mask:
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case X86::BI__builtin_ia32_vpermilps_mask:
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case X86::BI__builtin_ia32_extractf64x2_512_mask:
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case X86::BI__builtin_ia32_extracti64x2_512_mask:
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i = 1; l = 0; u = 3;
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break;
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case X86::BI__builtin_ia32_insertf32x8_mask:
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case X86::BI__builtin_ia32_inserti32x8_mask:
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case X86::BI__builtin_ia32_insertf64x4_mask:
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case X86::BI__builtin_ia32_inserti64x4_mask:
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case X86::BI__builtin_ia32_insertf64x2_256_mask:
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case X86::BI__builtin_ia32_inserti64x2_256_mask:
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case X86::BI__builtin_ia32_insertf32x4_256_mask:
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case X86::BI__builtin_ia32_inserti32x4_256_mask:
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i = 2; l = 0; u = 1;
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break;
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case X86::BI__builtin_ia32_sha1rnds4:
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i = 2;
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l = 0;
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u = 3;
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case X86::BI__builtin_ia32_shuf_f32x4_256_mask:
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case X86::BI__builtin_ia32_shuf_f64x2_256_mask:
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case X86::BI__builtin_ia32_shuf_i32x4_256_mask:
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case X86::BI__builtin_ia32_shuf_i64x2_256_mask:
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case X86::BI__builtin_ia32_shufpd128_mask:
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case X86::BI__builtin_ia32_insertf64x2_512_mask:
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case X86::BI__builtin_ia32_inserti64x2_512_mask:
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case X86::BI__builtin_ia32_insertf32x4_mask:
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case X86::BI__builtin_ia32_inserti32x4_mask:
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i = 2; l = 0; u = 3;
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break;
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case X86::BI__builtin_ia32_vpermil2pd:
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case X86::BI__builtin_ia32_vpermil2pd256:
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case X86::BI__builtin_ia32_vpermil2ps:
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case X86::BI__builtin_ia32_vpermil2ps256:
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i = 3;
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l = 0;
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u = 3;
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i = 3; l = 0; u = 3;
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break;
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case X86::BI__builtin_ia32_cmpb128_mask:
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case X86::BI__builtin_ia32_cmpw128_mask:
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@ -1365,36 +1394,6 @@ bool Sema::CheckX86BuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) {
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case X86::BI__builtin_ia32_ucmpw512_mask:
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case X86::BI__builtin_ia32_ucmpd512_mask:
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case X86::BI__builtin_ia32_ucmpq512_mask:
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i = 2;
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l = 0;
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u = 7;
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break;
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case X86::BI__builtin_ia32_roundps:
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case X86::BI__builtin_ia32_roundpd:
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case X86::BI__builtin_ia32_roundps256:
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case X86::BI__builtin_ia32_roundpd256:
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i = 1;
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l = 0;
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u = 15;
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break;
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case X86::BI__builtin_ia32_roundss:
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case X86::BI__builtin_ia32_roundsd:
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i = 2;
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l = 0;
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u = 15;
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break;
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case X86::BI__builtin_ia32_cmpps:
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case X86::BI__builtin_ia32_cmpss:
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case X86::BI__builtin_ia32_cmppd:
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case X86::BI__builtin_ia32_cmpsd:
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case X86::BI__builtin_ia32_cmpps256:
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case X86::BI__builtin_ia32_cmppd256:
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case X86::BI__builtin_ia32_cmpps512_mask:
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case X86::BI__builtin_ia32_cmppd512_mask:
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i = 2;
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l = 0;
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u = 31;
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break;
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case X86::BI__builtin_ia32_vpcomub:
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case X86::BI__builtin_ia32_vpcomuw:
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case X86::BI__builtin_ia32_vpcomud:
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@ -1403,9 +1402,218 @@ bool Sema::CheckX86BuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) {
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case X86::BI__builtin_ia32_vpcomw:
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case X86::BI__builtin_ia32_vpcomd:
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case X86::BI__builtin_ia32_vpcomq:
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i = 2;
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l = 0;
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u = 7;
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i = 2; l = 0; u = 7;
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break;
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case X86::BI__builtin_ia32_roundps:
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case X86::BI__builtin_ia32_roundpd:
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case X86::BI__builtin_ia32_roundps256:
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case X86::BI__builtin_ia32_roundpd256:
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case X86::BI__builtin_ia32_vpermilpd256_mask:
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case X86::BI__builtin_ia32_vpermilps256_mask:
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i = 1; l = 0; u = 15;
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break;
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case X86::BI__builtin_ia32_roundss:
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case X86::BI__builtin_ia32_roundsd:
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case X86::BI__builtin_ia32_rangepd128_mask:
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case X86::BI__builtin_ia32_rangepd256_mask:
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case X86::BI__builtin_ia32_rangepd512_mask:
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case X86::BI__builtin_ia32_rangeps128_mask:
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case X86::BI__builtin_ia32_rangeps256_mask:
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case X86::BI__builtin_ia32_rangeps512_mask:
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case X86::BI__builtin_ia32_getmantsd_round_mask:
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case X86::BI__builtin_ia32_getmantss_round_mask:
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case X86::BI__builtin_ia32_shufpd256_mask:
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i = 2; l = 0; u = 15;
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break;
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case X86::BI__builtin_ia32_cmpps:
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case X86::BI__builtin_ia32_cmpss:
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case X86::BI__builtin_ia32_cmppd:
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case X86::BI__builtin_ia32_cmpsd:
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case X86::BI__builtin_ia32_cmpps256:
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case X86::BI__builtin_ia32_cmppd256:
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case X86::BI__builtin_ia32_cmpps128_mask:
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case X86::BI__builtin_ia32_cmppd128_mask:
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case X86::BI__builtin_ia32_cmpps256_mask:
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case X86::BI__builtin_ia32_cmppd256_mask:
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case X86::BI__builtin_ia32_cmpps512_mask:
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case X86::BI__builtin_ia32_cmppd512_mask:
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case X86::BI__builtin_ia32_cmpsd_mask:
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case X86::BI__builtin_ia32_cmpss_mask:
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i = 2; l = 0; u = 31;
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break;
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case X86::BI__builtin_ia32_xabort:
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i = 0; l = -128; u = 255;
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break;
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case X86::BI__builtin_ia32_pshufw:
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case X86::BI__builtin_ia32_aeskeygenassist128:
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i = 1; l = -128; u = 255;
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break;
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case X86::BI__builtin_ia32_vcvtps2ph:
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case X86::BI__builtin_ia32_vcvtps2ph256:
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case X86::BI__builtin_ia32_vcvtps2ph512:
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case X86::BI__builtin_ia32_rndscaleps_128_mask:
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case X86::BI__builtin_ia32_rndscalepd_128_mask:
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case X86::BI__builtin_ia32_rndscaleps_256_mask:
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case X86::BI__builtin_ia32_rndscalepd_256_mask:
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case X86::BI__builtin_ia32_rndscaleps_mask:
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case X86::BI__builtin_ia32_rndscalepd_mask:
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case X86::BI__builtin_ia32_reducepd128_mask:
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case X86::BI__builtin_ia32_reducepd256_mask:
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case X86::BI__builtin_ia32_reducepd512_mask:
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case X86::BI__builtin_ia32_reduceps128_mask:
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case X86::BI__builtin_ia32_reduceps256_mask:
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case X86::BI__builtin_ia32_reduceps512_mask:
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case X86::BI__builtin_ia32_prold512_mask:
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case X86::BI__builtin_ia32_prolq512_mask:
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case X86::BI__builtin_ia32_prold128_mask:
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case X86::BI__builtin_ia32_prold256_mask:
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case X86::BI__builtin_ia32_prolq128_mask:
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case X86::BI__builtin_ia32_prolq256_mask:
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case X86::BI__builtin_ia32_prord128_mask:
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case X86::BI__builtin_ia32_prord256_mask:
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case X86::BI__builtin_ia32_prorq128_mask:
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case X86::BI__builtin_ia32_prorq256_mask:
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case X86::BI__builtin_ia32_pshufhw512_mask:
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case X86::BI__builtin_ia32_pshuflw512_mask:
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case X86::BI__builtin_ia32_pshufhw128_mask:
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case X86::BI__builtin_ia32_pshufhw256_mask:
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case X86::BI__builtin_ia32_pshuflw128_mask:
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case X86::BI__builtin_ia32_pshuflw256_mask:
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case X86::BI__builtin_ia32_psllwi512_mask:
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case X86::BI__builtin_ia32_psllwi128_mask:
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case X86::BI__builtin_ia32_psllwi256_mask:
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case X86::BI__builtin_ia32_psrldi128_mask:
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case X86::BI__builtin_ia32_psrldi256_mask:
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case X86::BI__builtin_ia32_psrldi512_mask:
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case X86::BI__builtin_ia32_psrlqi128_mask:
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case X86::BI__builtin_ia32_psrlqi256_mask:
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case X86::BI__builtin_ia32_psrlqi512_mask:
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case X86::BI__builtin_ia32_psrawi512_mask:
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case X86::BI__builtin_ia32_psrawi128_mask:
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case X86::BI__builtin_ia32_psrawi256_mask:
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case X86::BI__builtin_ia32_psrlwi512_mask:
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case X86::BI__builtin_ia32_psrlwi128_mask:
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case X86::BI__builtin_ia32_psrlwi256_mask:
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case X86::BI__builtin_ia32_vpermilpd512_mask:
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case X86::BI__builtin_ia32_vpermilps512_mask:
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case X86::BI__builtin_ia32_psradi128_mask:
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case X86::BI__builtin_ia32_psradi256_mask:
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case X86::BI__builtin_ia32_psradi512_mask:
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case X86::BI__builtin_ia32_psraqi128_mask:
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case X86::BI__builtin_ia32_psraqi256_mask:
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case X86::BI__builtin_ia32_psraqi512_mask:
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case X86::BI__builtin_ia32_pslldi128_mask:
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case X86::BI__builtin_ia32_pslldi256_mask:
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case X86::BI__builtin_ia32_pslldi512_mask:
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case X86::BI__builtin_ia32_psllqi128_mask:
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case X86::BI__builtin_ia32_psllqi256_mask:
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case X86::BI__builtin_ia32_psllqi512_mask:
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case X86::BI__builtin_ia32_permdf512_mask:
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case X86::BI__builtin_ia32_permdi512_mask:
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case X86::BI__builtin_ia32_permdf256_mask:
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case X86::BI__builtin_ia32_permdi256_mask:
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case X86::BI__builtin_ia32_fpclasspd128_mask:
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case X86::BI__builtin_ia32_fpclasspd256_mask:
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case X86::BI__builtin_ia32_fpclassps128_mask:
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case X86::BI__builtin_ia32_fpclassps256_mask:
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case X86::BI__builtin_ia32_fpclassps512_mask:
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case X86::BI__builtin_ia32_fpclasspd512_mask:
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case X86::BI__builtin_ia32_fpclasssd_mask:
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case X86::BI__builtin_ia32_fpclassss_mask:
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case X86::BI__builtin_ia32_pshufd512_mask:
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case X86::BI__builtin_ia32_pshufd256_mask:
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case X86::BI__builtin_ia32_pshufd128_mask:
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i = 1; l = 0; u = 255;
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break;
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case X86::BI__builtin_ia32_palignr:
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case X86::BI__builtin_ia32_insertps128:
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case X86::BI__builtin_ia32_dpps:
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case X86::BI__builtin_ia32_dppd:
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case X86::BI__builtin_ia32_dpps256:
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case X86::BI__builtin_ia32_mpsadbw128:
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case X86::BI__builtin_ia32_mpsadbw256:
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case X86::BI__builtin_ia32_pcmpistrm128:
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case X86::BI__builtin_ia32_pcmpistri128:
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case X86::BI__builtin_ia32_pcmpistria128:
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case X86::BI__builtin_ia32_pcmpistric128:
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case X86::BI__builtin_ia32_pcmpistrio128:
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case X86::BI__builtin_ia32_pcmpistris128:
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case X86::BI__builtin_ia32_pcmpistriz128:
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case X86::BI__builtin_ia32_pclmulqdq128:
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case X86::BI__builtin_ia32_vperm2f128_pd256:
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case X86::BI__builtin_ia32_vperm2f128_ps256:
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case X86::BI__builtin_ia32_vperm2f128_si256:
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case X86::BI__builtin_ia32_permti256:
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i = 2; l = -128; u = 255;
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break;
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case X86::BI__builtin_ia32_palignr128:
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case X86::BI__builtin_ia32_palignr256:
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case X86::BI__builtin_ia32_palignr128_mask:
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case X86::BI__builtin_ia32_palignr256_mask:
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case X86::BI__builtin_ia32_palignr512_mask:
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case X86::BI__builtin_ia32_alignq512_mask:
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case X86::BI__builtin_ia32_alignd512_mask:
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case X86::BI__builtin_ia32_alignd128_mask:
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case X86::BI__builtin_ia32_alignd256_mask:
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case X86::BI__builtin_ia32_alignq128_mask:
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case X86::BI__builtin_ia32_alignq256_mask:
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case X86::BI__builtin_ia32_vcomisd:
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case X86::BI__builtin_ia32_vcomiss:
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case X86::BI__builtin_ia32_shuf_f32x4_mask:
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case X86::BI__builtin_ia32_shuf_f64x2_mask:
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case X86::BI__builtin_ia32_shuf_i32x4_mask:
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case X86::BI__builtin_ia32_shuf_i64x2_mask:
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case X86::BI__builtin_ia32_shufpd512_mask:
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case X86::BI__builtin_ia32_shufps128_mask:
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case X86::BI__builtin_ia32_shufps256_mask:
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case X86::BI__builtin_ia32_shufps512_mask:
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case X86::BI__builtin_ia32_dbpsadbw128_mask:
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case X86::BI__builtin_ia32_dbpsadbw256_mask:
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case X86::BI__builtin_ia32_dbpsadbw512_mask:
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i = 2; l = 0; u = 255;
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break;
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case X86::BI__builtin_ia32_fixupimmpd512_mask:
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case X86::BI__builtin_ia32_fixupimmpd512_maskz:
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case X86::BI__builtin_ia32_fixupimmps512_mask:
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case X86::BI__builtin_ia32_fixupimmps512_maskz:
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case X86::BI__builtin_ia32_fixupimmsd_mask:
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case X86::BI__builtin_ia32_fixupimmsd_maskz:
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case X86::BI__builtin_ia32_fixupimmss_mask:
|
||||
case X86::BI__builtin_ia32_fixupimmss_maskz:
|
||||
case X86::BI__builtin_ia32_fixupimmpd128_mask:
|
||||
case X86::BI__builtin_ia32_fixupimmpd128_maskz:
|
||||
case X86::BI__builtin_ia32_fixupimmpd256_mask:
|
||||
case X86::BI__builtin_ia32_fixupimmpd256_maskz:
|
||||
case X86::BI__builtin_ia32_fixupimmps128_mask:
|
||||
case X86::BI__builtin_ia32_fixupimmps128_maskz:
|
||||
case X86::BI__builtin_ia32_fixupimmps256_mask:
|
||||
case X86::BI__builtin_ia32_fixupimmps256_maskz:
|
||||
case X86::BI__builtin_ia32_pternlogd512_mask:
|
||||
case X86::BI__builtin_ia32_pternlogd512_maskz:
|
||||
case X86::BI__builtin_ia32_pternlogq512_mask:
|
||||
case X86::BI__builtin_ia32_pternlogq512_maskz:
|
||||
case X86::BI__builtin_ia32_pternlogd128_mask:
|
||||
case X86::BI__builtin_ia32_pternlogd128_maskz:
|
||||
case X86::BI__builtin_ia32_pternlogd256_mask:
|
||||
case X86::BI__builtin_ia32_pternlogd256_maskz:
|
||||
case X86::BI__builtin_ia32_pternlogq128_mask:
|
||||
case X86::BI__builtin_ia32_pternlogq128_maskz:
|
||||
case X86::BI__builtin_ia32_pternlogq256_mask:
|
||||
case X86::BI__builtin_ia32_pternlogq256_maskz:
|
||||
i = 3; l = 0; u = 255;
|
||||
break;
|
||||
case X86::BI__builtin_ia32_pcmpestrm128:
|
||||
case X86::BI__builtin_ia32_pcmpestri128:
|
||||
case X86::BI__builtin_ia32_pcmpestria128:
|
||||
case X86::BI__builtin_ia32_pcmpestric128:
|
||||
case X86::BI__builtin_ia32_pcmpestrio128:
|
||||
case X86::BI__builtin_ia32_pcmpestris128:
|
||||
case X86::BI__builtin_ia32_pcmpestriz128:
|
||||
i = 4; l = -128; u = 255;
|
||||
break;
|
||||
case X86::BI__builtin_ia32_rndscalesd_round_mask:
|
||||
case X86::BI__builtin_ia32_rndscaless_round_mask:
|
||||
i = 4; l = 0; u = 255;
|
||||
break;
|
||||
}
|
||||
return SemaBuiltinConstantArgRange(TheCall, i, l, u);
|
||||
|
|
|
|||
|
|
@ -5090,97 +5090,97 @@ __m256i test_mm256_maskz_ternarylogic_epi64(__mmask8 __U, __m256i __A, __m256i _
|
|||
__m256 test_mm256_shuffle_f32x4(__m256 __A, __m256 __B) {
|
||||
// CHECK-LABEL: @test_mm256_shuffle_f32x4
|
||||
// CHECK: @llvm.x86.avx512.mask.shuf.f32x4
|
||||
return _mm256_shuffle_f32x4(__A, __B, 4);
|
||||
return _mm256_shuffle_f32x4(__A, __B, 3);
|
||||
}
|
||||
|
||||
__m256 test_mm256_mask_shuffle_f32x4(__m256 __W, __mmask8 __U, __m256 __A, __m256 __B) {
|
||||
// CHECK-LABEL: @test_mm256_mask_shuffle_f32x4
|
||||
// CHECK: @llvm.x86.avx512.mask.shuf.f32x4
|
||||
return _mm256_mask_shuffle_f32x4(__W, __U, __A, __B, 4);
|
||||
return _mm256_mask_shuffle_f32x4(__W, __U, __A, __B, 3);
|
||||
}
|
||||
|
||||
__m256 test_mm256_maskz_shuffle_f32x4(__mmask8 __U, __m256 __A, __m256 __B) {
|
||||
// CHECK-LABEL: @test_mm256_maskz_shuffle_f32x4
|
||||
// CHECK: @llvm.x86.avx512.mask.shuf.f32x4
|
||||
return _mm256_maskz_shuffle_f32x4(__U, __A, __B, 4);
|
||||
return _mm256_maskz_shuffle_f32x4(__U, __A, __B, 3);
|
||||
}
|
||||
|
||||
__m256d test_mm256_shuffle_f64x2(__m256d __A, __m256d __B) {
|
||||
// CHECK-LABEL: @test_mm256_shuffle_f64x2
|
||||
// CHECK: @llvm.x86.avx512.mask.shuf.f64x2
|
||||
return _mm256_shuffle_f64x2(__A, __B, 4);
|
||||
return _mm256_shuffle_f64x2(__A, __B, 3);
|
||||
}
|
||||
|
||||
__m256d test_mm256_mask_shuffle_f64x2(__m256d __W, __mmask8 __U, __m256d __A, __m256d __B) {
|
||||
// CHECK-LABEL: @test_mm256_mask_shuffle_f64x2
|
||||
// CHECK: @llvm.x86.avx512.mask.shuf.f64x2
|
||||
return _mm256_mask_shuffle_f64x2(__W, __U, __A, __B, 4);
|
||||
return _mm256_mask_shuffle_f64x2(__W, __U, __A, __B, 3);
|
||||
}
|
||||
|
||||
__m256d test_mm256_maskz_shuffle_f64x2(__mmask8 __U, __m256d __A, __m256d __B) {
|
||||
// CHECK-LABEL: @test_mm256_maskz_shuffle_f64x2
|
||||
// CHECK: @llvm.x86.avx512.mask.shuf.f64x2
|
||||
return _mm256_maskz_shuffle_f64x2(__U, __A, __B, 4);
|
||||
return _mm256_maskz_shuffle_f64x2(__U, __A, __B, 3);
|
||||
}
|
||||
|
||||
__m256i test_mm256_shuffle_i32x4(__m256i __A, __m256i __B) {
|
||||
// CHECK-LABEL: @test_mm256_shuffle_i32x4
|
||||
// CHECK: @llvm.x86.avx512.mask.shuf.i32x4
|
||||
return _mm256_shuffle_i32x4(__A, __B, 4);
|
||||
return _mm256_shuffle_i32x4(__A, __B, 3);
|
||||
}
|
||||
|
||||
__m256i test_mm256_mask_shuffle_i32x4(__m256i __W, __mmask8 __U, __m256i __A, __m256i __B) {
|
||||
// CHECK-LABEL: @test_mm256_mask_shuffle_i32x4
|
||||
// CHECK: @llvm.x86.avx512.mask.shuf.i32x4
|
||||
return _mm256_mask_shuffle_i32x4(__W, __U, __A, __B, 4);
|
||||
return _mm256_mask_shuffle_i32x4(__W, __U, __A, __B, 3);
|
||||
}
|
||||
|
||||
__m256i test_mm256_maskz_shuffle_i32x4(__mmask8 __U, __m256i __A, __m256i __B) {
|
||||
// CHECK-LABEL: @test_mm256_maskz_shuffle_i32x4
|
||||
// CHECK: @llvm.x86.avx512.mask.shuf.i32x4
|
||||
return _mm256_maskz_shuffle_i32x4(__U, __A, __B, 4);
|
||||
return _mm256_maskz_shuffle_i32x4(__U, __A, __B, 3);
|
||||
}
|
||||
|
||||
__m256i test_mm256_shuffle_i64x2(__m256i __A, __m256i __B) {
|
||||
// CHECK-LABEL: @test_mm256_shuffle_i64x2
|
||||
// CHECK: @llvm.x86.avx512.mask.shuf.i64x2
|
||||
return _mm256_shuffle_i64x2(__A, __B, 4);
|
||||
return _mm256_shuffle_i64x2(__A, __B, 3);
|
||||
}
|
||||
|
||||
__m256i test_mm256_mask_shuffle_i64x2(__m256i __W, __mmask8 __U, __m256i __A, __m256i __B) {
|
||||
// CHECK-LABEL: @test_mm256_mask_shuffle_i64x2
|
||||
// CHECK: @llvm.x86.avx512.mask.shuf.i64x2
|
||||
return _mm256_mask_shuffle_i64x2(__W, __U, __A, __B, 4);
|
||||
return _mm256_mask_shuffle_i64x2(__W, __U, __A, __B, 3);
|
||||
}
|
||||
|
||||
__m256i test_mm256_maskz_shuffle_i64x2(__mmask8 __U, __m256i __A, __m256i __B) {
|
||||
// CHECK-LABEL: @test_mm256_maskz_shuffle_i64x2
|
||||
// CHECK: @llvm.x86.avx512.mask.shuf.i64x2
|
||||
return _mm256_maskz_shuffle_i64x2(__U, __A, __B, 4);
|
||||
return _mm256_maskz_shuffle_i64x2(__U, __A, __B, 3);
|
||||
}
|
||||
|
||||
__m128d test_mm_mask_shuffle_pd(__m128d __W, __mmask8 __U, __m128d __A, __m128d __B) {
|
||||
// CHECK-LABEL: @test_mm_mask_shuffle_pd
|
||||
// CHECK: @llvm.x86.avx512.mask.shuf.pd.128
|
||||
return _mm_mask_shuffle_pd(__W, __U, __A, __B, 4);
|
||||
return _mm_mask_shuffle_pd(__W, __U, __A, __B, 3);
|
||||
}
|
||||
|
||||
__m128d test_mm_maskz_shuffle_pd(__mmask8 __U, __m128d __A, __m128d __B) {
|
||||
// CHECK-LABEL: @test_mm_maskz_shuffle_pd
|
||||
// CHECK: @llvm.x86.avx512.mask.shuf.pd.128
|
||||
return _mm_maskz_shuffle_pd(__U, __A, __B, 4);
|
||||
return _mm_maskz_shuffle_pd(__U, __A, __B, 3);
|
||||
}
|
||||
|
||||
__m256d test_mm256_mask_shuffle_pd(__m256d __W, __mmask8 __U, __m256d __A, __m256d __B) {
|
||||
// CHECK-LABEL: @test_mm256_mask_shuffle_pd
|
||||
// CHECK: @llvm.x86.avx512.mask.shuf.pd.256
|
||||
return _mm256_mask_shuffle_pd(__W, __U, __A, __B, 4);
|
||||
return _mm256_mask_shuffle_pd(__W, __U, __A, __B, 3);
|
||||
}
|
||||
|
||||
__m256d test_mm256_maskz_shuffle_pd(__mmask8 __U, __m256d __A, __m256d __B) {
|
||||
// CHECK-LABEL: @test_mm256_maskz_shuffle_pd
|
||||
// CHECK: @llvm.x86.avx512.mask.shuf.pd.256
|
||||
return _mm256_maskz_shuffle_pd(__U, __A, __B, 4);
|
||||
return _mm256_maskz_shuffle_pd(__U, __A, __B, 3);
|
||||
}
|
||||
|
||||
__m128 test_mm_mask_shuffle_ps(__m128 __W, __mmask8 __U, __m128 __A, __m128 __B) {
|
||||
|
|
|
|||
Loading…
Reference in New Issue