Added the follwoing 32-bit Thumb instructions for disassembly only:
o Parallel addition and subtraction, signed/unsigned o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8 o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16 o Signed multiply accumulate long (halfwords): SMLAL<x><y> o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X] o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X] llvm-svn: 97276
This commit is contained in:
Johnny Chen
parent
17d54920d7
commit
38e7bb6f34
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@ -1203,6 +1203,19 @@ class T2Iidxldst<bit signed, bits<2> opcod, bit load, bit pre,
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let Inst{8} = 1; // The W bit.
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}
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// Helper class for disassembly only
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// A6.3.16 & A6.3.17
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// T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
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class T2I_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops, dag iops,
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InstrItinClass itin, string opc, string asm, list<dag> pattern>
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: T2I<oops, iops, itin, opc, asm, pattern> {
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let Inst{31-27} = 0b11111;
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let Inst{26-24} = 0b011;
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let Inst{23} = long;
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let Inst{22-20} = op22_20;
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let Inst{7-4} = op7_4;
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}
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// Tv5Pat - Same as Pat<>, but requires V5T Thumb mode.
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class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> {
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list<Predicate> Predicates = [IsThumb1Only, HasV5T];
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@ -1586,9 +1586,9 @@ def UHSAX : AAI<0b01100111, 0b0101, "uhsax">;
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def UHSUB16 : AAI<0b01100111, 0b0111, "uhsub16">;
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def UHSUB8 : AAI<0b01100111, 0b1111, "uhsub8">;
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// Unsigned Sum of Absolute Difference [and Accumulate] -- for disassembly only
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// Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
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def USAD8 : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
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def USAD8 : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
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MulFrm /* for convenience */, NoItinerary, "usad8",
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"\t$dst, $a, $b", []>,
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Requires<[IsARM, HasV6]> {
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@ -1146,6 +1146,142 @@ def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
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def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
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(t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
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// A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
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// And Miscellaneous operations -- for disassembly only
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class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc>
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: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), NoItinerary, opc,
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"\t$dst, $a, $b", [/* For disassembly only; pattern left blank */]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0101;
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let Inst{22-20} = op22_20;
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let Inst{15-12} = 0b1111;
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let Inst{7-4} = op7_4;
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}
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// Saturating add/subtract -- for disassembly only
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def t2QADD : T2I_pam<0b000, 0b1000, "qadd">;
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def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
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def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
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def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
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def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd">;
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def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub">;
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def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
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def t2QSUB : T2I_pam<0b000, 0b1010, "qsub">;
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def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
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def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
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def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
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def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
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def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
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def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
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def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
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def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
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// Signed/Unsigned add/subtract -- for disassembly only
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def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
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def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
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def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
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def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
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def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
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def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
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def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
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def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
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def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
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def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
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def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
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def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
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// Signed/Unsigned halving add/subtract -- for disassembly only
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def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
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def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
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def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
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def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
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def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
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def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
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def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
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def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
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def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
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def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
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def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
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def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
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// Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
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def t2USAD8 : T2I_mac<0, 0b111, 0b0000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
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NoItinerary, "usad8", "\t$dst, $a, $b", []> {
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let Inst{15-12} = 0b1111;
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}
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def t2USADA8 : T2I_mac<0, 0b111, 0b0000, (outs GPR:$dst),
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(ins GPR:$a, GPR:$b, GPR:$acc), NoItinerary, "usada8",
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"\t$dst, $a, $b, $acc", []>;
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// Signed/Unsigned saturate -- for disassembly only
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def t2SSATlsl : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos,GPR:$a,i32imm:$shamt),
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NoItinerary, "ssat", "\t$dst, $bit_pos, $a, LSL $shamt",
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[/* For disassembly only; pattern left blank */]> {
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let Inst{31-27} = 0b11110;
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let Inst{25-22} = 0b1100;
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let Inst{20} = 0;
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let Inst{15} = 0;
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let Inst{21} = 0; // sh = '0'
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}
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def t2SSATasr : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos,GPR:$a,i32imm:$shamt),
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NoItinerary, "ssat", "\t$dst, $bit_pos, $a, ASR $shamt",
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[/* For disassembly only; pattern left blank */]> {
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let Inst{31-27} = 0b11110;
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let Inst{25-22} = 0b1100;
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let Inst{20} = 0;
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let Inst{15} = 0;
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let Inst{21} = 1; // sh = '1'
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}
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def t2SSAT16 : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a), NoItinerary,
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"ssat16", "\t$dst, $bit_pos, $a",
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[/* For disassembly only; pattern left blank */]> {
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let Inst{31-27} = 0b11110;
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let Inst{25-22} = 0b1100;
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let Inst{20} = 0;
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let Inst{15} = 0;
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let Inst{21} = 1; // sh = '1'
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let Inst{14-12} = 0b000; // imm3 = '000'
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let Inst{7-6} = 0b00; // imm2 = '00'
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}
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def t2USATlsl : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos,GPR:$a,i32imm:$shamt),
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NoItinerary, "usat", "\t$dst, $bit_pos, $a, LSL $shamt",
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[/* For disassembly only; pattern left blank */]> {
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let Inst{31-27} = 0b11110;
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let Inst{25-22} = 0b1110;
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let Inst{20} = 0;
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let Inst{15} = 0;
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let Inst{21} = 0; // sh = '0'
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}
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def t2USATasr : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos,GPR:$a,i32imm:$shamt),
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NoItinerary, "usat", "\t$dst, $bit_pos, $a, ASR $shamt",
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[/* For disassembly only; pattern left blank */]> {
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let Inst{31-27} = 0b11110;
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let Inst{25-22} = 0b1110;
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let Inst{20} = 0;
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let Inst{15} = 0;
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let Inst{21} = 1; // sh = '1'
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}
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def t2USAT16 : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a), NoItinerary,
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"usat16", "\t$dst, $bit_pos, $a",
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[/* For disassembly only; pattern left blank */]> {
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let Inst{31-27} = 0b11110;
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let Inst{25-22} = 0b1110;
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let Inst{20} = 0;
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let Inst{15} = 0;
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let Inst{21} = 1; // sh = '1'
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let Inst{14-12} = 0b000; // imm3 = '000'
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let Inst{7-6} = 0b00; // imm2 = '00'
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}
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//===----------------------------------------------------------------------===//
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// Shift and rotate Instructions.
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@ -1535,9 +1671,63 @@ multiclass T2I_smla<string opc, PatFrag opnode> {
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defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
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defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
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// TODO: Halfword multiple accumulate long: SMLAL<x><y>
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// TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
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// Halfword multiple accumulate long: SMLAL<x><y> -- for disassembly only
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def t2SMLALBB : T2I_mac<1, 0b100, 0b1000, (outs GPR:$ldst,GPR:$hdst),
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(ins GPR:$a,GPR:$b), IIC_iMAC64, "smlalbb", "\t$ldst, $hdst, $a, $b",
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[/* For disassembly only; pattern left blank */]>;
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def t2SMLALBT : T2I_mac<1, 0b100, 0b1001, (outs GPR:$ldst,GPR:$hdst),
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(ins GPR:$a,GPR:$b), IIC_iMAC64, "smlalbt", "\t$ldst, $hdst, $a, $b",
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[/* For disassembly only; pattern left blank */]>;
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def t2SMLALTB : T2I_mac<1, 0b100, 0b1010, (outs GPR:$ldst,GPR:$hdst),
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(ins GPR:$a,GPR:$b), IIC_iMAC64, "smlaltb", "\t$ldst, $hdst, $a, $b",
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[/* For disassembly only; pattern left blank */]>;
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def t2SMLALTT : T2I_mac<1, 0b100, 0b1011, (outs GPR:$ldst,GPR:$hdst),
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(ins GPR:$a,GPR:$b), IIC_iMAC64, "smlaltt", "\t$ldst, $hdst, $a, $b",
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[/* For disassembly only; pattern left blank */]>;
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// Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
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// These are for disassembly only.
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def t2SMUAD : T2I_mac<0, 0b010, 0b0000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
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IIC_iMAC32, "smuad", "\t$dst, $a, $b", []> {
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let Inst{15-12} = 0b1111;
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}
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def t2SMUADX : T2I_mac<0, 0b010, 0b0001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
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IIC_iMAC32, "smuadx", "\t$dst, $a, $b", []> {
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let Inst{15-12} = 0b1111;
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}
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def t2SMUSD : T2I_mac<0, 0b100, 0b0000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
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IIC_iMAC32, "smusd", "\t$dst, $a, $b", []> {
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let Inst{15-12} = 0b1111;
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}
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def t2SMUSDX : T2I_mac<0, 0b100, 0b0001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
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IIC_iMAC32, "smusdx", "\t$dst, $a, $b", []> {
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let Inst{15-12} = 0b1111;
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}
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def t2SMLAD : T2I_mac<0, 0b010, 0b0000, (outs GPR:$dst),
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(ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC32, "smlad",
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"\t$dst, $a, $b, $acc", []>;
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def t2SMLADX : T2I_mac<0, 0b010, 0b0001, (outs GPR:$dst),
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(ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC32, "smladx",
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"\t$dst, $a, $b, $acc", []>;
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def t2SMLSD : T2I_mac<0, 0b100, 0b0000, (outs GPR:$dst),
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(ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC32, "smlsd",
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"\t$dst, $a, $b, $acc", []>;
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def t2SMLSDX : T2I_mac<0, 0b100, 0b0001, (outs GPR:$dst),
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(ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC32, "smlsdx",
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"\t$dst, $a, $b, $acc", []>;
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def t2SMLALD : T2I_mac<1, 0b100, 0b1100, (outs GPR:$ldst,GPR:$hdst),
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(ins GPR:$a,GPR:$b), IIC_iMAC64, "smlald",
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"\t$ldst, $hdst, $a, $b", []>;
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def t2SMLALDX : T2I_mac<1, 0b100, 0b1101, (outs GPR:$ldst,GPR:$hdst),
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(ins GPR:$a,GPR:$b), IIC_iMAC64, "smlaldx",
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"\t$ldst, $hdst, $a, $b", []>;
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def t2SMLSLD : T2I_mac<1, 0b101, 0b1100, (outs GPR:$ldst,GPR:$hdst),
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(ins GPR:$a,GPR:$b), IIC_iMAC64, "smlsld",
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"\t$ldst, $hdst, $a, $b", []>;
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def t2SMLSLDX : T2I_mac<1, 0b101, 0b1101, (outs GPR:$ldst,GPR:$hdst),
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(ins GPR:$a,GPR:$b), IIC_iMAC64, "smlsldx",
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"\t$ldst, $hdst, $a, $b", []>;
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//===----------------------------------------------------------------------===//
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// Misc. Arithmetic Instructions.
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