[risc-v] Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
Summary: This clang-tidy check is looking for unsigned integer variables whose initializer starts with an implicit cast from llvm::Register and changes the type of the variable to llvm::Register (dropping the llvm:: where possible). Depends on D65919 Reviewers: lenary Subscribers: jholewinski, MatzeB, qcolombet, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, wdng, nhaehnle, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, javed.absar, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, tpr, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, Jim, s.egerton, llvm-commits Tags: #llvm Differential Revision for full review was: https://reviews.llvm.org/D65962 llvm-svn: 368629
This commit is contained in:
Daniel Sanders
parent
5ae66e56cf
commit
3836874dbb
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@ -235,10 +235,10 @@ static void doAtomicBinOpExpansion(const RISCVInstrInfo *TII, MachineInstr &MI,
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MachineBasicBlock *LoopMBB,
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MachineBasicBlock *DoneMBB,
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AtomicRMWInst::BinOp BinOp, int Width) {
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unsigned DestReg = MI.getOperand(0).getReg();
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unsigned ScratchReg = MI.getOperand(1).getReg();
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unsigned AddrReg = MI.getOperand(2).getReg();
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unsigned IncrReg = MI.getOperand(3).getReg();
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Register DestReg = MI.getOperand(0).getReg();
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Register ScratchReg = MI.getOperand(1).getReg();
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Register AddrReg = MI.getOperand(2).getReg();
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Register IncrReg = MI.getOperand(3).getReg();
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AtomicOrdering Ordering =
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static_cast<AtomicOrdering>(MI.getOperand(4).getImm());
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@ -297,11 +297,11 @@ static void doMaskedAtomicBinOpExpansion(
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MachineBasicBlock *ThisMBB, MachineBasicBlock *LoopMBB,
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MachineBasicBlock *DoneMBB, AtomicRMWInst::BinOp BinOp, int Width) {
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assert(Width == 32 && "Should never need to expand masked 64-bit operations");
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unsigned DestReg = MI.getOperand(0).getReg();
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unsigned ScratchReg = MI.getOperand(1).getReg();
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unsigned AddrReg = MI.getOperand(2).getReg();
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unsigned IncrReg = MI.getOperand(3).getReg();
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unsigned MaskReg = MI.getOperand(4).getReg();
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Register DestReg = MI.getOperand(0).getReg();
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Register ScratchReg = MI.getOperand(1).getReg();
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Register AddrReg = MI.getOperand(2).getReg();
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Register IncrReg = MI.getOperand(3).getReg();
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Register MaskReg = MI.getOperand(4).getReg();
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AtomicOrdering Ordering =
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static_cast<AtomicOrdering>(MI.getOperand(5).getImm());
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@ -436,12 +436,12 @@ bool RISCVExpandPseudo::expandAtomicMinMaxOp(
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DoneMBB->transferSuccessors(&MBB);
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MBB.addSuccessor(LoopHeadMBB);
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unsigned DestReg = MI.getOperand(0).getReg();
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unsigned Scratch1Reg = MI.getOperand(1).getReg();
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unsigned Scratch2Reg = MI.getOperand(2).getReg();
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unsigned AddrReg = MI.getOperand(3).getReg();
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unsigned IncrReg = MI.getOperand(4).getReg();
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unsigned MaskReg = MI.getOperand(5).getReg();
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Register DestReg = MI.getOperand(0).getReg();
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Register Scratch1Reg = MI.getOperand(1).getReg();
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Register Scratch2Reg = MI.getOperand(2).getReg();
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Register AddrReg = MI.getOperand(3).getReg();
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Register IncrReg = MI.getOperand(4).getReg();
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Register MaskReg = MI.getOperand(5).getReg();
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bool IsSigned = BinOp == AtomicRMWInst::Min || BinOp == AtomicRMWInst::Max;
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AtomicOrdering Ordering =
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static_cast<AtomicOrdering>(MI.getOperand(IsSigned ? 7 : 6).getImm());
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@ -549,11 +549,11 @@ bool RISCVExpandPseudo::expandAtomicCmpXchg(
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DoneMBB->transferSuccessors(&MBB);
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MBB.addSuccessor(LoopHeadMBB);
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unsigned DestReg = MI.getOperand(0).getReg();
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unsigned ScratchReg = MI.getOperand(1).getReg();
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unsigned AddrReg = MI.getOperand(2).getReg();
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unsigned CmpValReg = MI.getOperand(3).getReg();
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unsigned NewValReg = MI.getOperand(4).getReg();
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Register DestReg = MI.getOperand(0).getReg();
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Register ScratchReg = MI.getOperand(1).getReg();
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Register AddrReg = MI.getOperand(2).getReg();
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Register CmpValReg = MI.getOperand(3).getReg();
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Register NewValReg = MI.getOperand(4).getReg();
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AtomicOrdering Ordering =
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static_cast<AtomicOrdering>(MI.getOperand(IsMasked ? 6 : 5).getImm());
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@ -582,7 +582,7 @@ bool RISCVExpandPseudo::expandAtomicCmpXchg(
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// lr.w dest, (addr)
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// and scratch, dest, mask
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// bne scratch, cmpval, done
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unsigned MaskReg = MI.getOperand(5).getReg();
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Register MaskReg = MI.getOperand(5).getReg();
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BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg)
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.addReg(AddrReg);
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BuildMI(LoopHeadMBB, DL, TII->get(RISCV::AND), ScratchReg)
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@ -629,7 +629,7 @@ bool RISCVExpandPseudo::expandAuipcInstPair(
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MachineInstr &MI = *MBBI;
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DebugLoc DL = MI.getDebugLoc();
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unsigned DestReg = MI.getOperand(0).getReg();
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Register DestReg = MI.getOperand(0).getReg();
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const MachineOperand &Symbol = MI.getOperand(1);
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MachineBasicBlock *NewMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
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@ -82,7 +82,7 @@ void RISCVFrameLowering::adjustReg(MachineBasicBlock &MBB,
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Opc = RISCV::SUB;
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}
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unsigned ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
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Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
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TII->movImm32(MBB, MBBI, DL, ScratchReg, Val, Flag);
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BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg)
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.addReg(SrcReg)
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@ -230,7 +230,7 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
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// To find the instruction restoring FP from stack.
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for (auto &I = LastFrameDestroy; I != MBBI; ++I) {
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if (I->mayLoad() && I->getOperand(0).isReg()) {
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unsigned DestReg = I->getOperand(0).getReg();
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Register DestReg = I->getOperand(0).getReg();
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if (DestReg == FPReg) {
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// If there is frame pointer, after restoring $fp registers, we
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// need adjust CFA to ($sp - FPOffset).
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@ -663,7 +663,7 @@ SDValue RISCVTargetLowering::lowerFRAMEADDR(SDValue Op,
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MachineFunction &MF = DAG.getMachineFunction();
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MachineFrameInfo &MFI = MF.getFrameInfo();
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MFI.setFrameAddressIsTaken(true);
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unsigned FrameReg = RI.getFrameRegister(MF);
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Register FrameReg = RI.getFrameRegister(MF);
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int XLenInBytes = Subtarget.getXLen() / 8;
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EVT VT = Op.getValueType();
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@ -1111,9 +1111,9 @@ MachineBasicBlock *emitReadCycleWidePseudo(MachineInstr &MI,
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BB->addSuccessor(LoopMBB);
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MachineRegisterInfo &RegInfo = MF.getRegInfo();
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unsigned ReadAgainReg = RegInfo.createVirtualRegister(&RISCV::GPRRegClass);
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unsigned LoReg = MI.getOperand(0).getReg();
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unsigned HiReg = MI.getOperand(1).getReg();
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Register ReadAgainReg = RegInfo.createVirtualRegister(&RISCV::GPRRegClass);
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Register LoReg = MI.getOperand(0).getReg();
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Register HiReg = MI.getOperand(1).getReg();
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DebugLoc DL = MI.getDebugLoc();
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const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
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@ -1148,9 +1148,9 @@ static MachineBasicBlock *emitSplitF64Pseudo(MachineInstr &MI,
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DebugLoc DL = MI.getDebugLoc();
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const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
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const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo();
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unsigned LoReg = MI.getOperand(0).getReg();
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unsigned HiReg = MI.getOperand(1).getReg();
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unsigned SrcReg = MI.getOperand(2).getReg();
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Register LoReg = MI.getOperand(0).getReg();
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Register HiReg = MI.getOperand(1).getReg();
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Register SrcReg = MI.getOperand(2).getReg();
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const TargetRegisterClass *SrcRC = &RISCV::FPR64RegClass;
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int FI = MF.getInfo<RISCVMachineFunctionInfo>()->getMoveF64FrameIndex();
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@ -1180,9 +1180,9 @@ static MachineBasicBlock *emitBuildPairF64Pseudo(MachineInstr &MI,
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DebugLoc DL = MI.getDebugLoc();
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const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
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const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo();
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unsigned DstReg = MI.getOperand(0).getReg();
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unsigned LoReg = MI.getOperand(1).getReg();
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unsigned HiReg = MI.getOperand(2).getReg();
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Register DstReg = MI.getOperand(0).getReg();
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Register LoReg = MI.getOperand(1).getReg();
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Register HiReg = MI.getOperand(2).getReg();
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const TargetRegisterClass *DstRC = &RISCV::FPR64RegClass;
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int FI = MF.getInfo<RISCVMachineFunctionInfo>()->getMoveF64FrameIndex();
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@ -1241,8 +1241,8 @@ static MachineBasicBlock *emitSelectPseudo(MachineInstr &MI,
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// previous selects in the sequence.
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// These conditions could be further relaxed. See the X86 target for a
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// related approach and more information.
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unsigned LHS = MI.getOperand(1).getReg();
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unsigned RHS = MI.getOperand(2).getReg();
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Register LHS = MI.getOperand(1).getReg();
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Register RHS = MI.getOperand(2).getReg();
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auto CC = static_cast<ISD::CondCode>(MI.getOperand(3).getImm());
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SmallVector<MachineInstr *, 4> SelectDebugValues;
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@ -1699,7 +1699,7 @@ static SDValue unpackFromRegLoc(SelectionDAG &DAG, SDValue Chain,
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break;
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}
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unsigned VReg = RegInfo.createVirtualRegister(RC);
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Register VReg = RegInfo.createVirtualRegister(RC);
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RegInfo.addLiveIn(VA.getLocReg(), VReg);
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Val = DAG.getCopyFromReg(Chain, DL, VReg, LocVT);
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@ -1777,7 +1777,7 @@ static SDValue unpackF64OnRV32DSoftABI(SelectionDAG &DAG, SDValue Chain,
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assert(VA.isRegLoc() && "Expected register VA assignment");
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unsigned LoVReg = RegInfo.createVirtualRegister(&RISCV::GPRRegClass);
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Register LoVReg = RegInfo.createVirtualRegister(&RISCV::GPRRegClass);
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RegInfo.addLiveIn(VA.getLocReg(), LoVReg);
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SDValue Lo = DAG.getCopyFromReg(Chain, DL, LoVReg, MVT::i32);
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SDValue Hi;
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@ -1789,7 +1789,7 @@ static SDValue unpackF64OnRV32DSoftABI(SelectionDAG &DAG, SDValue Chain,
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MachinePointerInfo::getFixedStack(MF, FI));
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} else {
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// Second half of f64 is passed in another GPR.
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unsigned HiVReg = RegInfo.createVirtualRegister(&RISCV::GPRRegClass);
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Register HiVReg = RegInfo.createVirtualRegister(&RISCV::GPRRegClass);
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RegInfo.addLiveIn(VA.getLocReg() + 1, HiVReg);
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Hi = DAG.getCopyFromReg(Chain, DL, HiVReg, MVT::i32);
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}
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@ -1912,7 +1912,7 @@ SDValue RISCVTargetLowering::LowerFormalArguments(
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// to the vararg save area.
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for (unsigned I = Idx; I < ArgRegs.size();
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++I, VaArgOffset += XLenInBytes) {
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const unsigned Reg = RegInfo.createVirtualRegister(RC);
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const Register Reg = RegInfo.createVirtualRegister(RC);
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RegInfo.addLiveIn(ArgRegs[I], Reg);
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SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, XLenVT);
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FI = MFI.CreateFixedObject(XLenInBytes, VaArgOffset, true);
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@ -2100,7 +2100,7 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
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SDValue Lo = SplitF64.getValue(0);
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SDValue Hi = SplitF64.getValue(1);
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unsigned RegLo = VA.getLocReg();
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Register RegLo = VA.getLocReg();
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RegsToPass.push_back(std::make_pair(RegLo, Lo));
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if (RegLo == RISCV::X17) {
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@ -2328,7 +2328,7 @@ RISCVTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
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DAG.getVTList(MVT::i32, MVT::i32), Val);
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SDValue Lo = SplitF64.getValue(0);
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SDValue Hi = SplitF64.getValue(1);
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unsigned RegLo = VA.getLocReg();
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Register RegLo = VA.getLocReg();
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unsigned RegHi = RegLo + 1;
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Chain = DAG.getCopyToReg(Chain, DL, RegLo, Lo, Glue);
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Glue = Chain.getValue(1);
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@ -372,7 +372,7 @@ unsigned RISCVInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
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// FIXME: A virtual register must be used initially, as the register
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// scavenger won't work with empty blocks (SIInstrInfo::insertIndirectBranch
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// uses the same workaround).
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unsigned ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
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Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
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auto II = MBB.end();
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MachineInstr &LuiMI = *BuildMI(MBB, II, DL, get(RISCV::LUI), ScratchReg)
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@ -85,7 +85,7 @@ bool RISCVMergeBaseOffsetOpt::detectLuiAddiGlobal(MachineInstr &HiLUI,
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HiLUI.getOperand(1).getOffset() != 0 ||
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!MRI->hasOneUse(HiLUI.getOperand(0).getReg()))
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return false;
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unsigned HiLuiDestReg = HiLUI.getOperand(0).getReg();
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Register HiLuiDestReg = HiLUI.getOperand(0).getReg();
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LoADDI = MRI->use_begin(HiLuiDestReg)->getParent();
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if (LoADDI->getOpcode() != RISCV::ADDI ||
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LoADDI->getOperand(2).getTargetFlags() != RISCVII::MO_LO ||
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@ -135,8 +135,8 @@ bool RISCVMergeBaseOffsetOpt::matchLargeOffset(MachineInstr &TailAdd,
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unsigned GAReg,
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int64_t &Offset) {
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assert((TailAdd.getOpcode() == RISCV::ADD) && "Expected ADD instruction!");
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unsigned Rs = TailAdd.getOperand(1).getReg();
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unsigned Rt = TailAdd.getOperand(2).getReg();
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Register Rs = TailAdd.getOperand(1).getReg();
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Register Rt = TailAdd.getOperand(2).getReg();
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unsigned Reg = Rs == GAReg ? Rt : Rs;
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// Can't fold if the register has more than one use.
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@ -178,7 +178,7 @@ bool RISCVMergeBaseOffsetOpt::matchLargeOffset(MachineInstr &TailAdd,
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bool RISCVMergeBaseOffsetOpt::detectAndFoldOffset(MachineInstr &HiLUI,
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MachineInstr &LoADDI) {
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unsigned DestReg = LoADDI.getOperand(0).getReg();
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Register DestReg = LoADDI.getOperand(0).getReg();
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assert(MRI->hasOneUse(DestReg) && "expected one use for LoADDI");
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// LoADDI has only one use.
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MachineInstr &Tail = *MRI->use_begin(DestReg)->getParent();
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@ -232,7 +232,7 @@ bool RISCVMergeBaseOffsetOpt::detectAndFoldOffset(MachineInstr &HiLUI,
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return false;
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// Register defined by LoADDI should be used in the base part of the
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// load\store instruction. Otherwise, no folding possible.
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unsigned BaseAddrReg = Tail.getOperand(1).getReg();
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Register BaseAddrReg = Tail.getOperand(1).getReg();
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if (DestReg != BaseAddrReg)
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return false;
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MachineOperand &TailImmOp = Tail.getOperand(2);
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@ -109,7 +109,7 @@ void RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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assert(isInt<32>(Offset) && "Int32 expected");
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// The offset won't fit in an immediate, so use a scratch register instead
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// Modify Offset and FrameReg appropriately
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unsigned ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
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Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
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TII->movImm32(MBB, II, DL, ScratchReg, Offset);
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BuildMI(MBB, II, DL, TII->get(RISCV::ADD), ScratchReg)
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.addReg(FrameReg)
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