[DAGCombiner] Don't allow addcarry if the carry producer is illegal.
getAsCarry() checks that the input argument is a carry-producing node before allowing a transformation to addcarry. This patch adds a check to make sure that the carry-producing node is legal. If it is not, it may not remain in a form that is manageable by the target backend. The test case caused a compilation failure during instruction selection for this reason on SystemZ. Patch by Ulrich Weigand. Review: Sanjay Patel https://reviews.llvm.org/D59822 llvm-svn: 357052
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@ -2336,6 +2336,10 @@ static SDValue getAsCarry(const TargetLowering &TLI, SDValue V) {
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V.getOpcode() != ISD::UADDO && V.getOpcode() != ISD::USUBO)
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V.getOpcode() != ISD::UADDO && V.getOpcode() != ISD::USUBO)
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return SDValue();
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return SDValue();
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EVT VT = V.getNode()->getValueType(0);
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if (!TLI.isOperationLegalOrCustom(V.getOpcode(), VT))
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return SDValue();
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// If the result is masked, then no matter what kind of bool it is we can
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// If the result is masked, then no matter what kind of bool it is we can
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// return. If it isn't, then we need to make sure the bool type is either 0 or
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// return. If it isn't, then we need to make sure the bool type is either 0 or
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// 1 and not other values.
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// 1 and not other values.
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@ -0,0 +1,35 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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;
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; Test that DAGCombiner does not produce an addcarry node if the carry
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; producer is not legal. This can happen e.g. with an uaddo with a type
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; that is not legal.
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;
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; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 < %s | FileCheck %s
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define void @fun(i16 %arg0, i16* %src, i32* %dst) {
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; CHECK-LABEL: fun:
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; CHECK: # %bb.0: # %bb
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; CHECK-NEXT: llhr %r0, %r2
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; CHECK-NEXT: llh %r2, 0(%r3)
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; CHECK-NEXT: chi %r0, 9616
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; CHECK-NEXT: lhi %r1, 0
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; CHECK-NEXT: lochil %r1, 1
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; CHECK-NEXT: afi %r2, 65535
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; CHECK-NEXT: llhr %r3, %r2
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; CHECK-NEXT: lhi %r0, 0
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; CHECK-NEXT: cr %r3, %r2
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; CHECK-NEXT: lochilh %r0, 1
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; CHECK-NEXT: ar %r0, %r1
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; CHECK-NEXT: st %r0, 0(%r4)
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; CHECK-NEXT: br %r14
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bb:
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%tmp = icmp ult i16 %arg0, 9616
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%tmp1 = zext i1 %tmp to i32
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%tmp2 = load i16, i16* %src
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%tmp3 = add i16 %tmp2, -1
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%tmp4 = icmp ne i16 %tmp2, 0
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%tmp5 = zext i1 %tmp4 to i32
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%tmp6 = add nuw nsw i32 %tmp5, %tmp1
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store i32 %tmp6, i32* %dst
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ret void
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}
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