[AMDGPU] Collapse adjacent SI_END_CF
Add a pass to remove redundant S_OR_B64 instructions enabling lanes in the exec. If two SI_END_CF (lowered as S_OR_B64) come together without any vector instructions between them we can only keep outer SI_END_CF, given that CFG is structured and exec bits of the outer end statement are always not less than exec bit of the inner one. This needs to be done before the RA to eliminate saved exec bits registers but after register coalescer to have no vector registers copies in between of different end cf statements. Differential Revision: https://reviews.llvm.org/D35967 llvm-svn: 309762
This commit is contained in:
Stanislav Mekhanoshin
parent
81ea122121
commit
37e7f959c0
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@ -44,6 +44,7 @@ FunctionPass *createSIShrinkInstructionsPass();
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FunctionPass *createSILoadStoreOptimizerPass();
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FunctionPass *createSIWholeQuadModePass();
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FunctionPass *createSIFixControlFlowLiveIntervalsPass();
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FunctionPass *createSIOptimizeExecMaskingPreRAPass();
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FunctionPass *createSIFixSGPRCopiesPass();
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FunctionPass *createSIMemoryLegalizerPass();
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FunctionPass *createSIDebuggerInsertNopsPass();
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@ -121,6 +122,9 @@ extern char &AMDGPUUnifyMetadataID;
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void initializeSIFixControlFlowLiveIntervalsPass(PassRegistry&);
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extern char &SIFixControlFlowLiveIntervalsID;
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void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry&);
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extern char &SIOptimizeExecMaskingPreRAID;
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void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry&);
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extern char &AMDGPUAnnotateUniformValuesPassID;
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@ -142,6 +142,7 @@ extern "C" void LLVMInitializeAMDGPUTarget() {
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initializeSIPeepholeSDWAPass(*PR);
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initializeSIShrinkInstructionsPass(*PR);
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initializeSIFixControlFlowLiveIntervalsPass(*PR);
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initializeSIOptimizeExecMaskingPreRAPass(*PR);
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initializeSILoadStoreOptimizerPass(*PR);
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initializeAMDGPUAlwaysInlinePass(*PR);
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initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
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@ -781,6 +782,9 @@ void GCNPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
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}
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void GCNPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
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if (getOptLevel() > CodeGenOpt::None)
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insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
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// This needs to be run directly before register allocation because earlier
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// passes might recompute live intervals.
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insertPass(&MachineSchedulerID, &SIFixControlFlowLiveIntervalsID);
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@ -97,6 +97,7 @@ add_llvm_target(AMDGPUCodeGen
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SIMachineScheduler.cpp
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SIMemoryLegalizer.cpp
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SIOptimizeExecMasking.cpp
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SIOptimizeExecMaskingPreRA.cpp
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SIPeepholeSDWA.cpp
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SIRegisterInfo.cpp
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SIShrinkInstructions.cpp
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@ -0,0 +1,159 @@
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//===-- SIOptimizeExecMaskingPreRA.cpp ------------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief This pass removes redundant S_OR_B64 instructions enabling lanes in
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/// the exec. If two SI_END_CF (lowered as S_OR_B64) come together without any
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/// vector instructions between them we can only keep outer SI_END_CF, given
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/// that CFG is structured and exec bits of the outer end statement are always
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/// not less than exec bit of the inner one.
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///
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/// This needs to be done before the RA to eliminate saved exec bits registers
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/// but after register coalescer to have no vector registers copies in between
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/// of different end cf statements.
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///
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "AMDGPUSubtarget.h"
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#include "SIInstrInfo.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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using namespace llvm;
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#define DEBUG_TYPE "si-optimize-exec-masking-pre-ra"
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namespace {
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class SIOptimizeExecMaskingPreRA : public MachineFunctionPass {
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public:
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static char ID;
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public:
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SIOptimizeExecMaskingPreRA() : MachineFunctionPass(ID) {
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initializeSIOptimizeExecMaskingPreRAPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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StringRef getPassName() const override {
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return "SI optimize exec mask operations pre-RA";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.addRequired<LiveIntervals>();
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AU.setPreservesAll();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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};
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} // End anonymous namespace.
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INITIALIZE_PASS_BEGIN(SIOptimizeExecMaskingPreRA, DEBUG_TYPE,
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"SI optimize exec mask operations pre-RA", false, false)
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INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
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INITIALIZE_PASS_END(SIOptimizeExecMaskingPreRA, DEBUG_TYPE,
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"SI optimize exec mask operations pre-RA", false, false)
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char SIOptimizeExecMaskingPreRA::ID = 0;
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char &llvm::SIOptimizeExecMaskingPreRAID = SIOptimizeExecMaskingPreRA::ID;
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FunctionPass *llvm::createSIOptimizeExecMaskingPreRAPass() {
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return new SIOptimizeExecMaskingPreRA();
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}
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static bool isEndCF(const MachineInstr& MI, const SIRegisterInfo* TRI) {
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return MI.getOpcode() == AMDGPU::S_OR_B64 &&
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MI.modifiesRegister(AMDGPU::EXEC, TRI);
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}
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static bool isFullExecCopy(const MachineInstr& MI) {
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return MI.isFullCopy() && MI.getOperand(1).getReg() == AMDGPU::EXEC;
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}
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static unsigned getOrNonExecReg(const MachineInstr &MI,
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const SIInstrInfo &TII) {
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auto Op = TII.getNamedOperand(MI, AMDGPU::OpName::src1);
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if (Op->isReg() && Op->getReg() != AMDGPU::EXEC)
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return Op->getReg();
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Op = TII.getNamedOperand(MI, AMDGPU::OpName::src0);
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if (Op->isReg() && Op->getReg() != AMDGPU::EXEC)
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return Op->getReg();
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return AMDGPU::NoRegister;
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}
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static MachineInstr* getOrExecSource(const MachineInstr &MI,
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const SIInstrInfo &TII,
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const MachineRegisterInfo &MRI) {
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auto SavedExec = getOrNonExecReg(MI, TII);
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if (SavedExec == AMDGPU::NoRegister)
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return nullptr;
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auto SaveExecInst = MRI.getUniqueVRegDef(SavedExec);
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if (!SaveExecInst || !isFullExecCopy(*SaveExecInst))
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return nullptr;
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return SaveExecInst;
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}
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bool SIOptimizeExecMaskingPreRA::runOnMachineFunction(MachineFunction &MF) {
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if (skipFunction(*MF.getFunction()))
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return false;
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const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
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const SIRegisterInfo *TRI = ST.getRegisterInfo();
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const SIInstrInfo *TII = ST.getInstrInfo();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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LiveIntervals *LIS = &getAnalysis<LiveIntervals>();
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bool Changed = false;
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for (MachineBasicBlock &MBB : MF) {
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auto Lead = MBB.begin(), E = MBB.end();
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if (MBB.succ_size() != 1 || Lead == E || !isEndCF(*Lead, TRI))
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continue;
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const MachineBasicBlock* Succ = *MBB.succ_begin();
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if (!MBB.isLayoutSuccessor(Succ))
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continue;
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auto I = std::next(Lead);
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for ( ; I != E; ++I)
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if (!TII->isSALU(*I) || I->readsRegister(AMDGPU::EXEC, TRI))
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break;
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if (I != E)
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continue;
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const auto NextLead = Succ->begin();
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if (NextLead == Succ->end() || !isEndCF(*NextLead, TRI) ||
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!getOrExecSource(*NextLead, *TII, MRI))
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continue;
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DEBUG(dbgs() << "Redundant EXEC = S_OR_B64 found: " << *Lead << '\n');
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unsigned SaveExecReg = getOrNonExecReg(*Lead, *TII);
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LIS->RemoveMachineInstrFromMaps(*Lead);
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Lead->eraseFromParent();
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if (SaveExecReg) {
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LIS->removeInterval(SaveExecReg);
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LIS->createAndComputeVirtRegInterval(SaveExecReg);
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}
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Changed = true;
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}
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if (Changed) {
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// Recompute liveness for both reg units of exec.
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LIS->removeRegUnit(*MCRegUnitIterator(AMDGPU::EXEC_LO, TRI));
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LIS->removeRegUnit(*MCRegUnitIterator(AMDGPU::EXEC_HI, TRI));
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}
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return Changed;
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}
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@ -0,0 +1,188 @@
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: {{^}}simple_nested_if:
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; GCN: s_and_saveexec_b64 [[SAVEEXEC:s\[[0-9:]+\]]]
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; GCN-NEXT: ; mask branch [[ENDIF:BB[0-9_]+]]
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; GCN-NEXT: s_cbranch_execz [[ENDIF]]
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; GCN: s_and_saveexec_b64
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; GCN-NEXT: ; mask branch [[ENDIF]]
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; GCN-NEXT: {{^BB[0-9_]+}}:
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; GCN: store_dword
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; GCN-NEXT: {{^}}[[ENDIF]]:
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; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC]]
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; GCN-NEXT: s_endpgm
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define amdgpu_kernel void @simple_nested_if(i32 addrspace(1)* nocapture %arg) {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%tmp1 = icmp ugt i32 %tmp, 1
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br i1 %tmp1, label %bb.outer.then, label %bb.outer.end
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bb.outer.then: ; preds = %bb
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%tmp4 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %tmp
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store i32 0, i32 addrspace(1)* %tmp4, align 4
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%tmp5 = icmp eq i32 %tmp, 2
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br i1 %tmp5, label %bb.outer.end, label %bb.inner.then
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bb.inner.then: ; preds = %bb.outer.then
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%tmp7 = add i32 %tmp, 1
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%tmp9 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %tmp7
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store i32 1, i32 addrspace(1)* %tmp9, align 4
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br label %bb.outer.end
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bb.outer.end: ; preds = %bb.outer.then, %bb.inner.then, %bb
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ret void
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}
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; GCN-LABEL: {{^}}uncollapsable_nested_if:
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; GCN: s_and_saveexec_b64 [[SAVEEXEC_OUTER:s\[[0-9:]+\]]]
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; GCN-NEXT: ; mask branch [[ENDIF_OUTER:BB[0-9_]+]]
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; GCN-NEXT: s_cbranch_execz [[ENDIF_OUTER]]
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; GCN: s_and_saveexec_b64 [[SAVEEXEC_INNER:s\[[0-9:]+\]]]
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; GCN-NEXT: ; mask branch [[ENDIF_INNER:BB[0-9_]+]]
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; GCN-NEXT: {{^BB[0-9_]+}}:
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; GCN: store_dword
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; GCN-NEXT: {{^}}[[ENDIF_INNER]]:
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; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC_INNER]]
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; GCN: store_dword
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; GCN-NEXT: {{^}}[[ENDIF_OUTER]]:
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; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC_OUTER]]
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; GCN-NEXT: s_endpgm
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define amdgpu_kernel void @uncollapsable_nested_if(i32 addrspace(1)* nocapture %arg) {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%tmp1 = icmp ugt i32 %tmp, 1
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br i1 %tmp1, label %bb.outer.then, label %bb.outer.end
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bb.outer.then: ; preds = %bb
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%tmp4 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %tmp
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store i32 0, i32 addrspace(1)* %tmp4, align 4
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%tmp5 = icmp eq i32 %tmp, 2
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br i1 %tmp5, label %bb.inner.end, label %bb.inner.then
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bb.inner.then: ; preds = %bb.outer.then
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%tmp7 = add i32 %tmp, 1
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%tmp8 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %tmp7
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store i32 1, i32 addrspace(1)* %tmp8, align 4
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br label %bb.inner.end
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bb.inner.end: ; preds = %bb.inner.then, %bb.outer.then
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%tmp9 = add i32 %tmp, 2
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%tmp10 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %tmp9
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store i32 2, i32 addrspace(1)* %tmp10, align 4
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br label %bb.outer.end
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bb.outer.end: ; preds = %bb.inner.then, %bb
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ret void
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}
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; GCN-LABEL: {{^}}nested_if_if_else:
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; GCN: s_and_saveexec_b64 [[SAVEEXEC_OUTER:s\[[0-9:]+\]]]
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; GCN-NEXT: ; mask branch [[ENDIF_OUTER:BB[0-9_]+]]
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; GCN-NEXT: s_cbranch_execz [[ENDIF_OUTER]]
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; GCN: s_and_saveexec_b64 [[SAVEEXEC_INNER:s\[[0-9:]+\]]]
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; GCN-NEXT: s_xor_b64 [[SAVEEXEC_INNER2:s\[[0-9:]+\]]], exec, [[SAVEEXEC_INNER]]
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; GCN-NEXT: ; mask branch [[THEN_INNER:BB[0-9_]+]]
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; GCN-NEXT: {{^BB[0-9_]+}}:
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; GCN: store_dword
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; GCN-NEXT: {{^}}[[THEN_INNER]]:
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; GCN-NEXT: s_or_saveexec_b64 [[SAVEEXEC_INNER3:s\[[0-9:]+\]]], [[SAVEEXEC_INNER2]]
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; GCN-NEXT: s_xor_b64 exec, exec, [[SAVEEXEC_INNER3]]
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; GCN-NEXT: ; mask branch [[ENDIF_OUTER]]
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; GCN: store_dword
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; GCN-NEXT: {{^}}[[ENDIF_OUTER]]:
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; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC_OUTER]]
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; GCN-NEXT: s_endpgm
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define amdgpu_kernel void @nested_if_if_else(i32 addrspace(1)* nocapture %arg) {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%tmp1 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %tmp
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store i32 0, i32 addrspace(1)* %tmp1, align 4
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%tmp2 = icmp ugt i32 %tmp, 1
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br i1 %tmp2, label %bb.outer.then, label %bb.outer.end
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bb.outer.then: ; preds = %bb
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%tmp5 = icmp eq i32 %tmp, 2
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br i1 %tmp5, label %bb.then, label %bb.else
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bb.then: ; preds = %bb.outer.then
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%tmp3 = add i32 %tmp, 1
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%tmp4 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %tmp3
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store i32 1, i32 addrspace(1)* %tmp4, align 4
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br label %bb.outer.end
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bb.else: ; preds = %bb.outer.then
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%tmp7 = add i32 %tmp, 2
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%tmp9 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %tmp7
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store i32 2, i32 addrspace(1)* %tmp9, align 4
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br label %bb.outer.end
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bb.outer.end: ; preds = %bb, %bb.then, %bb.else
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ret void
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}
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; GCN-LABEL: {{^}}nested_if_else_if:
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; GCN: s_and_saveexec_b64 [[SAVEEXEC_OUTER:s\[[0-9:]+\]]]
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; GCN-NEXT: s_xor_b64 [[SAVEEXEC_OUTER2:s\[[0-9:]+\]]], exec, [[SAVEEXEC_OUTER]]
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; GCN-NEXT: ; mask branch [[THEN_OUTER:BB[0-9_]+]]
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; GCN-NEXT: s_cbranch_execz [[THEN_OUTER]]
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; GCN-NEXT: {{^BB[0-9_]+}}:
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; GCN: store_dword
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; GCN-NEXT: s_and_saveexec_b64 [[SAVEEXEC_INNER_IF_OUTER_ELSE:s\[[0-9:]+\]]]
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; GCN-NEXT: ; mask branch [[THEN_OUTER_FLOW:BB[0-9_]+]]
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; GCN-NEXT: {{^BB[0-9_]+}}:
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; GCN: store_dword
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; GCN-NEXT: {{^}}[[THEN_OUTER_FLOW]]:
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; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC_INNER_IF_OUTER_ELSE]]
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; GCN-NEXT: {{^}}[[THEN_OUTER]]:
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; GCN-NEXT: s_or_saveexec_b64 [[SAVEEXEC_OUTER3:s\[[0-9:]+\]]], [[SAVEEXEC_OUTER2]]
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; GCN-NEXT: s_xor_b64 exec, exec, [[SAVEEXEC_OUTER3]]
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; GCN-NEXT: ; mask branch [[ENDIF_OUTER:BB[0-9_]+]]
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; GCN-NEXT: s_cbranch_execz [[ENDIF_OUTER]]
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; GCN-NEXT: {{^BB[0-9_]+}}:
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; GCN: store_dword
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; GCN-NEXT: s_and_saveexec_b64 [[SAVEEXEC_INNER_IF_OUTER_THEN:s\[[0-9:]+\]]]
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; GCN-NEXT: ; mask branch [[ENDIF_INNER_OUTER_THEN:BB[0-9_]+]]
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; GCN-NEXT: {{^BB[0-9_]+}}:
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; GCN: store_dword
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; GCN-NEXT: {{^}}[[ENDIF_INNER_OUTER_THEN]]:
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; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC_INNER_IF_OUTER_THEN]]
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; GCN-NEXT: {{^}}[[ENDIF_OUTER]]:
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; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC_OUTER3]]
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; GCN-NEXT: s_endpgm
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define amdgpu_kernel void @nested_if_else_if(i32 addrspace(1)* nocapture %arg) {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%tmp1 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %tmp
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store i32 0, i32 addrspace(1)* %tmp1, align 4
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%cc1 = icmp ugt i32 %tmp, 1
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br i1 %cc1, label %bb.outer.then, label %bb.outer.else
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bb.outer.then:
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%tmp2 = getelementptr inbounds i32, i32 addrspace(1)* %tmp1, i32 1
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store i32 1, i32 addrspace(1)* %tmp2, align 4
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%cc2 = icmp eq i32 %tmp, 2
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br i1 %cc2, label %bb.inner.then, label %bb.outer.end
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||||
bb.inner.then:
|
||||
%tmp3 = getelementptr inbounds i32, i32 addrspace(1)* %tmp1, i32 2
|
||||
store i32 2, i32 addrspace(1)* %tmp3, align 4
|
||||
br label %bb.outer.end
|
||||
|
||||
bb.outer.else:
|
||||
%tmp4 = getelementptr inbounds i32, i32 addrspace(1)* %tmp1, i32 3
|
||||
store i32 3, i32 addrspace(1)* %tmp4, align 4
|
||||
%cc3 = icmp eq i32 %tmp, 2
|
||||
br i1 %cc3, label %bb.inner.then2, label %bb.outer.end
|
||||
|
||||
bb.inner.then2:
|
||||
%tmp5 = getelementptr inbounds i32, i32 addrspace(1)* %tmp1, i32 4
|
||||
store i32 4, i32 addrspace(1)* %tmp5, align 4
|
||||
br label %bb.outer.end
|
||||
|
||||
bb.outer.end:
|
||||
ret void
|
||||
}
|
||||
|
||||
declare i32 @llvm.amdgcn.workitem.id.x() #0
|
||||
|
||||
attributes #0 = { nounwind readnone speculatable }
|
||||
Loading…
Reference in New Issue