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ARM load/store optimizer: Compute BaseKill correctly. 

This adds some code back that was deleted in r92053. The location of the
last merged memory operation needs to be kept up-to-date since MemOps
may be in a different order to the original instruction stream to
allow merging (since registers need to be in ascending order). Also
simplify the logic to determine BaseKill using findRegisterUseOperandIdx
to use an equivalent function call instead.

llvm-svn: 215728
This commit is contained in:
Moritz Roth 2014-08-15 17:00:20 +00:00
parent 5df8603dfd
commit 378a43bfe0
1 changed files with 11 additions and 5 deletions
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16
llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
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@ -721,7 +721,7 @@ ARMLoadStoreOpt::MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex,
unsigned PRegNum = PMO.isUndef() ? UINT_MAX : TRI->getEncodingValue(PReg);
unsigned Count = 1;
unsigned Limit = ~0U;
bool BaseKill = false;
// vldm / vstm limit are 32 for S variants, 16 for D variants.
switch (Opcode) {
@ -760,18 +760,24 @@ ARMLoadStoreOpt::MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex,
++Count;
} else {
// Can't merge this in. Try merge the earlier ones first.
MergeOpsUpdate(MBB, MemOps, SIndex, i, insertAfter, SOffset,
Base, false, Opcode, Pred, PredReg, Scratch, dl, Merges);
// We need to compute BaseKill here because the MemOps may have been
// reordered.
BaseKill = Loc->killsRegister(Base);
MergeOpsUpdate(MBB, MemOps, SIndex, i, insertAfter, SOffset, Base,
BaseKill, Opcode, Pred, PredReg, Scratch, dl, Merges);
MergeLDR_STR(MBB, i, Base, Opcode, Size, Pred, PredReg, Scratch,
MemOps, Merges);
return;
}
if (MemOps[i].Position > MemOps[insertAfter].Position)
if (MemOps[i].Position > MemOps[insertAfter].Position) {
insertAfter = i;
Loc = MemOps[i].MBBI;
}
}
bool BaseKill = Loc->findRegisterUseOperandIdx(Base, true) != -1;
BaseKill = Loc->killsRegister(Base);
MergeOpsUpdate(MBB, MemOps, SIndex, MemOps.size(), insertAfter, SOffset,
Base, BaseKill, Opcode, Pred, PredReg, Scratch, dl, Merges);
}