[AMDGPU] Handle OR as operand of raw load/store
Summary: Use isBaseWithConstantOffset() which handles OR as an operand to llvm.amdgcn.raw.buffer.load and llvm.amdgcn.raw.buffer.store. Change-Id: Ifefb9dc5ded8710d333df07ab1900b230e33539a Reviewers: nhaehnle, mareko, arsenm Reviewed By: arsenm Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D55999 llvm-svn: 350208
This commit is contained in:
Piotr Sobczak
parent
176388c973
commit
378131bae0
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@ -6005,11 +6005,13 @@ std::pair<SDValue, SDValue> SITargetLowering::splitBufferOffsets(
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const unsigned MaxImm = 4095;
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SDValue N0 = Offset;
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ConstantSDNode *C1 = nullptr;
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if (N0.getOpcode() == ISD::ADD) {
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if ((C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))))
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N0 = N0.getOperand(0);
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} else if ((C1 = dyn_cast<ConstantSDNode>(N0)))
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if ((C1 = dyn_cast<ConstantSDNode>(N0)))
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N0 = SDValue();
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else if (DAG.isBaseWithConstantOffset(N0)) {
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C1 = cast<ConstantSDNode>(N0.getOperand(1));
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N0 = N0.getOperand(0);
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}
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if (C1) {
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unsigned ImmOffset = C1->getZExtValue();
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@ -97,12 +97,12 @@ entry:
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ret float %val
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}
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;CHECK-LABEL: {{^}}buffer_load_x1_offen_merged:
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;CHECK-LABEL: {{^}}buffer_load_x1_offen_merged_and:
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;CHECK-NEXT: %bb.
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;CHECK-NEXT: buffer_load_dwordx4 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:4
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;CHECK-NEXT: buffer_load_dwordx2 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:28
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;CHECK: s_waitcnt
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define amdgpu_ps void @buffer_load_x1_offen_merged(<4 x i32> inreg %rsrc, i32 %a) {
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define amdgpu_ps void @buffer_load_x1_offen_merged_and(<4 x i32> inreg %rsrc, i32 %a) {
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main_body:
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%a1 = add i32 %a, 4
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%a2 = add i32 %a, 8
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@ -121,6 +121,32 @@ main_body:
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_load_x1_offen_merged_or:
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;CHECK-NEXT: %bb.
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;CHECK-NEXT: v_lshlrev_b32_e32 v{{[0-9]}}, 6, v0
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;CHECK-NEXT: buffer_load_dwordx4 v[{{[0-9]}}:{{[0-9]}}], v{{[0-9]}}, s[0:3], 0 offen offset:4
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;CHECK-NEXT: buffer_load_dwordx2 v[{{[0-9]}}:{{[0-9]}}], v{{[0-9]}}, s[0:3], 0 offen offset:28
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;CHECK: s_waitcnt
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define amdgpu_ps void @buffer_load_x1_offen_merged_or(<4 x i32> inreg %rsrc, i32 %inp) {
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main_body:
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%a = shl i32 %inp, 6
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%a1 = or i32 %a, 4
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%a2 = or i32 %a, 8
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%a3 = or i32 %a, 12
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%a4 = or i32 %a, 16
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%a5 = or i32 %a, 28
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%a6 = or i32 %a, 32
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%r1 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a1, i32 0, i32 0)
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%r2 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a2, i32 0, i32 0)
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%r3 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a3, i32 0, i32 0)
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%r4 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a4, i32 0, i32 0)
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%r5 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a5, i32 0, i32 0)
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%r6 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a6, i32 0, i32 0)
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true)
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_load_x1_offen_merged_glc_slc:
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;CHECK-NEXT: %bb.
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;CHECK-NEXT: buffer_load_dwordx2 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:4{{$}}
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@ -146,11 +172,11 @@ main_body:
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_load_x2_offen_merged:
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;CHECK-LABEL: {{^}}buffer_load_x2_offen_merged_and:
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;CHECK-NEXT: %bb.
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;CHECK-NEXT: buffer_load_dwordx4 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:4
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;CHECK: s_waitcnt
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define amdgpu_ps void @buffer_load_x2_offen_merged(<4 x i32> inreg %rsrc, i32 %a) {
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define amdgpu_ps void @buffer_load_x2_offen_merged_and(<4 x i32> inreg %rsrc, i32 %a) {
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main_body:
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%a1 = add i32 %a, 4
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%a2 = add i32 %a, 12
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@ -164,6 +190,26 @@ main_body:
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_load_x2_offen_merged_or:
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;CHECK-NEXT: %bb.
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;CHECK-NEXT: v_lshlrev_b32_e32 v{{[0-9]}}, 4, v0
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;CHECK-NEXT: buffer_load_dwordx4 v[{{[0-9]}}:{{[0-9]}}], v{{[0-9]}}, s[0:3], 0 offen offset:4
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;CHECK: s_waitcnt
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define amdgpu_ps void @buffer_load_x2_offen_merged_or(<4 x i32> inreg %rsrc, i32 %inp) {
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main_body:
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%a = shl i32 %inp, 4
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%a1 = add i32 %a, 4
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%a2 = add i32 %a, 12
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%vr1 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 %a1, i32 0, i32 0)
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%vr2 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 %a2, i32 0, i32 0)
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%r1 = extractelement <2 x float> %vr1, i32 0
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%r2 = extractelement <2 x float> %vr1, i32 1
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%r3 = extractelement <2 x float> %vr2, i32 0
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%r4 = extractelement <2 x float> %vr2, i32 1
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_load_x1_offset_merged:
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;CHECK-NEXT: %bb.
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;CHECK-NEXT: buffer_load_dwordx4 v[{{[0-9]}}:{{[0-9]}}], off, s[0:3], 0 offset:4
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@ -67,11 +67,11 @@ main_body:
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_store_x1_offen_merged:
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;CHECK-LABEL: {{^}}buffer_store_x1_offen_merged_and:
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;CHECK-NOT: s_waitcnt
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;CHECK-DAG: buffer_store_dwordx4 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:4
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;CHECK-DAG: buffer_store_dwordx2 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:28
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define amdgpu_ps void @buffer_store_x1_offen_merged(<4 x i32> inreg %rsrc, i32 %a, float %v1, float %v2, float %v3, float %v4, float %v5, float %v6) {
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define amdgpu_ps void @buffer_store_x1_offen_merged_and(<4 x i32> inreg %rsrc, i32 %a, float %v1, float %v2, float %v3, float %v4, float %v5, float %v6) {
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%a1 = add i32 %a, 4
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%a2 = add i32 %a, 8
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%a3 = add i32 %a, 12
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@ -87,6 +87,28 @@ define amdgpu_ps void @buffer_store_x1_offen_merged(<4 x i32> inreg %rsrc, i32 %
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_store_x1_offen_merged_or:
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;CHECK-NOT: s_waitcnt
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;CHECK-DAG: buffer_store_dwordx4 v[{{[0-9]}}:{{[0-9]}}], v{{[0-9]}}, s[0:3], 0 offen offset:4
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;CHECK-DAG: buffer_store_dwordx2 v[{{[0-9]}}:{{[0-9]}}], v{{[0-9]}}, s[0:3], 0 offen offset:28
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define amdgpu_ps void @buffer_store_x1_offen_merged_or(<4 x i32> inreg %rsrc, i32 %inp, float %v1, float %v2, float %v3, float %v4, float %v5, float %v6) {
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%a = shl i32 %inp, 6
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%a1 = add i32 %a, 4
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%a2 = add i32 %a, 8
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%a3 = add i32 %a, 12
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%a4 = add i32 %a, 16
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%a5 = add i32 %a, 28
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%a6 = add i32 %a, 32
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call void @llvm.amdgcn.raw.buffer.store.f32(float %v1, <4 x i32> %rsrc, i32 %a1, i32 0, i32 0)
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call void @llvm.amdgcn.raw.buffer.store.f32(float %v2, <4 x i32> %rsrc, i32 %a2, i32 0, i32 0)
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call void @llvm.amdgcn.raw.buffer.store.f32(float %v3, <4 x i32> %rsrc, i32 %a3, i32 0, i32 0)
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call void @llvm.amdgcn.raw.buffer.store.f32(float %v4, <4 x i32> %rsrc, i32 %a4, i32 0, i32 0)
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call void @llvm.amdgcn.raw.buffer.store.f32(float %v5, <4 x i32> %rsrc, i32 %a5, i32 0, i32 0)
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call void @llvm.amdgcn.raw.buffer.store.f32(float %v6, <4 x i32> %rsrc, i32 %a6, i32 0, i32 0)
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_store_x1_offen_merged_glc_slc:
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;CHECK-NOT: s_waitcnt
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;CHECK-DAG: buffer_store_dwordx2 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:4{{$}}
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@ -108,10 +130,22 @@ define amdgpu_ps void @buffer_store_x1_offen_merged_glc_slc(<4 x i32> inreg %rsr
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_store_x2_offen_merged:
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;CHECK-LABEL: {{^}}buffer_store_x2_offen_merged_and:
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;CHECK-NOT: s_waitcnt
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;CHECK: buffer_store_dwordx4 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:4
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define amdgpu_ps void @buffer_store_x2_offen_merged(<4 x i32> inreg %rsrc, i32 %a, <2 x float> %v1, <2 x float> %v2) {
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define amdgpu_ps void @buffer_store_x2_offen_merged_and(<4 x i32> inreg %rsrc, i32 %a, <2 x float> %v1, <2 x float> %v2) {
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%a1 = add i32 %a, 4
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%a2 = add i32 %a, 12
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call void @llvm.amdgcn.raw.buffer.store.v2f32(<2 x float> %v1, <4 x i32> %rsrc, i32 %a1, i32 0, i32 0)
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call void @llvm.amdgcn.raw.buffer.store.v2f32(<2 x float> %v2, <4 x i32> %rsrc, i32 %a2, i32 0, i32 0)
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_store_x2_offen_merged_or:
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;CHECK-NOT: s_waitcnt
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;CHECK: buffer_store_dwordx4 v[{{[0-9]}}:{{[0-9]}}], v{{[0-9]}}, s[0:3], 0 offen offset:4
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define amdgpu_ps void @buffer_store_x2_offen_merged_or(<4 x i32> inreg %rsrc, i32 %inp, <2 x float> %v1, <2 x float> %v2) {
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%a = shl i32 %inp, 4
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%a1 = add i32 %a, 4
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%a2 = add i32 %a, 12
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call void @llvm.amdgcn.raw.buffer.store.v2f32(<2 x float> %v1, <4 x i32> %rsrc, i32 %a1, i32 0, i32 0)
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